coreboot-gerrit May 2021

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Change in coreboot[master]: treewide: Kconfig: drop `default n` for bool options
by Michael Niewöhner (Code Review) 04 May '21

04 May '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52812 ) Change subject: treewide: Kconfig: drop `default n` for bool options ...................................................................... Patch Set 1: Code-Review-1 (1 comment) This change is ready for review. Patchset: PS1: -1 see parent -- To view, visit https://review.coreboot.org/c/coreboot/+/52812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieea378502f12345e12d3dd954102d6cbf59d2732 Gerrit-Change-Number: 52812 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 04 May 2021 09:01:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: Kconfig: replace `def_bool n` by `bool`
by Michael Niewöhner (Code Review) 04 May '21

04 May '21

Attention is currently required from: Martin Roth, Werner Zeh. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52809 ) Change subject: treewide: Kconfig: replace `def_bool n` by `bool` ...................................................................... Patch Set 3: Code-Review-1 (1 comment) This change is ready for review. Patchset: PS3: > The def_bool n is not the same as bool and accepting the default of n. def_bool *SETS* the default, and a later default of 'y' will not update it. Thank you for bringing that up. I've tested and confirmed that. The first `default` will stick. That also means, the order is important. -- To view, visit https://review.coreboot.org/c/coreboot/+/52809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e89c66d18b7b3a5ac425eacea10df8c013814f Gerrit-Change-Number: 52809 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 04 May 2021 09:00:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add mtcmos init support
by Rex-BC Chen (Code Review) 04 May '21

04 May '21

Attention is currently required from: Hung-Te Lin, Weiyi Lu. Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52882 to review the following change. Change subject: soc/mediatek/mt8195: Add mtcmos init support ...................................................................... soc/mediatek/mt8195: Add mtcmos init support Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f --- M src/soc/mediatek/common/include/soc/mtcmos.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/spm.h A src/soc/mediatek/mt8195/mtcmos.c 5 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/52882/1 diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index 0e0e32a..20de4ea 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -8,8 +8,11 @@ u32 pwr_sta_mask; u32 sram_pdn_mask; u32 sram_ack_mask; + u32 caps; }; +#define SCPD_SRAM_ISO (1U << 0) + void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index 17a464f..6be7b1c 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -33,6 +33,12 @@ while (read32(pd->pwr_con) & pd->sram_ack_mask) continue; + + if (pd->caps & SCPD_SRAM_ISO) { + setbits32(pd->pwr_con, SRAM_ISOINT_B); + udelay(1); + clrbits32(pd->pwr_con, SRAM_CKISO); + } } void mtcmos_display_power_on(void) diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 0c5b9cf..796c335 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index c90e632..319509a 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -4,8 +4,13 @@ #define SOC_MEDIATEK_MT8195_SPM_H #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <types.h> +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + struct mtk_spm_regs { u32 poweron_config_set; u32 spm_power_on_val0; @@ -528,9 +533,54 @@ u32 spm_pmsr_len_con2; }; +check_member(mtk_spm_regs, pwr_status, 0x016c); +check_member(mtk_spm_regs, audio_pwr_con, 0x0358); check_member(mtk_spm_regs, ap_mdsrc_req, 0x043c); check_member(mtk_spm_regs, ulposc_con, 0x644); static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->vppsys0_pwr_con, + .pwr_sta_mask = 0x1 << 11, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, + { + .pwr_con = &mtk_spm->vdosys0_pwr_con, + .pwr_sta_mask = 0x1 << 13, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, + { + .pwr_con = &mtk_spm->vppsys1_pwr_con, + .pwr_sta_mask = 0x1 << 12, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, + { + .pwr_con = &mtk_spm->vdosys1_pwr_con, + .pwr_sta_mask = 0x1 << 14, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->adsp_pwr_con, + .pwr_sta_mask = 0x1 << 10, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + .caps = SCPD_SRAM_ISO, + }, + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = 0x1 << 8, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, +}; + #endif /* SOC_MEDIATEK_MT8195_SPM_H */ diff --git a/src/soc/mediatek/mt8195/mtcmos.c b/src/soc/mediatek/mt8195/mtcmos.c new file mode 100644 index 0000000..e194441 --- /dev/null +++ b/src/soc/mediatek/mt8195/mtcmos.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/mtcmos.h> + +enum { + VPPSYS0_PROT_STEP_6_MASK = 0x00100000, + VPPSYS0_PROT_STEP_5_MASK = 0x0007F8FF, + VPPSYS0_PROT_STEP_4_MASK = 0x00800000, + VPPSYS0_PROT_STEP_3_MASK = 0x01600300, + VPPSYS0_PROT_STEP_2_MASK = 0x80381DC7, + VPPSYS0_PROT_STEP_1_MASK = 0x00000400, + + VDOSYS0_PROT_STEP_5_MASK = 0x00200000, + VDOSYS0_PROT_STEP_4_MASK = 0x3FC00000, + VDOSYS0_PROT_STEP_3_MASK = 0x00000040, + VDOSYS0_PROT_STEP_2_MASK = 0x00800000, + VDOSYS0_PROT_STEP_1_MASK = 0x403E6238, + + VPPSYS1_PROT_STEP_3_MASK = 0x000400C0, + VPPSYS1_PROT_STEP_2_MASK = 0x00800000, + VPPSYS1_PROT_STEP_1_MASK = 0x000001E0, + + VDOSYS1_PROT_STEP_3_MASK = 0x00000400, + VDOSYS1_PROT_STEP_2_MASK = 0x00400000, + VDOSYS1_PROT_STEP_1_MASK = 0xC0000000, + + AUDIO_PROT_STEP_1_MASK = 0x00000600, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VPPSYS0_PROT_STEP_6_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_5_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_4_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS0_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VDOSYS0_PROT_STEP_5_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_4_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VDOSYS0_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VDOSYS0_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS1_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VDOSYS1_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2, + AUDIO_PROT_STEP_1_MASK); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Gerrit-Change-Number: 52882 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Move the power domain data under each SoC
by Rex-BC Chen (Code Review) 04 May '21

04 May '21

Attention is currently required from: Weiyi Lu. Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52881 to review the following change. Change subject: soc/mediatek: Move the power domain data under each SoC ...................................................................... soc/mediatek: Move the power domain data under each SoC In follow-up patches, we need to set multiple power domains to power on the display and audio on MT8195. Move the power domain data under each SoC and make power_on() API to support multiple settings. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I8c3d19f1e9a4e516d674d68989ad509f37e5b593 --- M src/soc/mediatek/common/include/soc/mtcmos.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8173/include/soc/spm.h M src/soc/mediatek/mt8183/include/soc/spm.h M src/soc/mediatek/mt8192/include/soc/spm.h 5 files changed, 71 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52881/1 diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index d8cb9f5..0e0e32a 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -3,6 +3,13 @@ #ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__ #define __SOC_MEDIATEK_COMMON_MTCMOS_H__ +struct power_domain_data { + void *pwr_con; + u32 pwr_sta_mask; + u32 sram_pdn_mask; + u32 sram_ack_mask; +}; + void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index cfd148c..17a464f 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -1,16 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <delay.h> #include <device/mmio.h> -#include <soc/mtcmos.h> #include <soc/spm.h> -struct power_domain_data { - void *pwr_con; - u32 pwr_sta_mask; - u32 sram_pdn_mask; - u32 sram_ack_mask; -}; - enum { SRAM_ISOINT_B = 1U << 6, SRAM_CKISO = 1U << 5, @@ -44,24 +37,16 @@ void mtcmos_display_power_on(void) { - static const struct power_domain_data disp = { - .pwr_con = &mtk_spm->dis_pwr_con, - .pwr_sta_mask = DISP_PWR_STA_MASK, - .sram_pdn_mask = DISP_SRAM_PDN_MASK, - .sram_ack_mask = DISP_SRAM_ACK_MASK, - }; + int i; - mtcmos_power_on(&disp); + for (i = 0; i < ARRAY_SIZE(disp); i++) + mtcmos_power_on(&disp[i]); } void mtcmos_audio_power_on(void) { - static const struct power_domain_data audio = { - .pwr_con = &mtk_spm->audio_pwr_con, - .pwr_sta_mask = AUDIO_PWR_STA_MASK, - .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, - .sram_ack_mask = AUDIO_SRAM_ACK_MASK, - }; + int i; - mtcmos_power_on(&audio); + for (i = 0; i < ARRAY_SIZE(audio); i++) + mtcmos_power_on(&audio[i]); } diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index efc04d1..64b33c8 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -4,6 +4,7 @@ #define __SOC_MEDIATEK_MT8173_SPM_H__ #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <stddef.h> enum { @@ -152,4 +153,22 @@ static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = DISP_PWR_STA_MASK, + .sram_pdn_mask = DISP_SRAM_PDN_MASK, + .sram_ack_mask = DISP_SRAM_ACK_MASK, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = AUDIO_PWR_STA_MASK, + .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, + .sram_ack_mask = AUDIO_SRAM_ACK_MASK, + }, +}; + #endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */ diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 327355a..d5663be 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_SPM_H #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <types.h> /* SPM READ/WRITE CFG */ @@ -580,4 +581,22 @@ int spm_init(void); +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = DISP_PWR_STA_MASK, + .sram_pdn_mask = DISP_SRAM_PDN_MASK, + .sram_ack_mask = DISP_SRAM_ACK_MASK, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = AUDIO_PWR_STA_MASK, + .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, + .sram_ack_mask = AUDIO_SRAM_ACK_MASK, + }, +}; + #endif /* SOC_MEDIATEK_MT8183_SPM_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index 8f69bf7..d99ca65 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_SPM_H #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <stdint.h> #include <types.h> @@ -674,4 +675,22 @@ int spm_init(void); +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = DISP_PWR_STA_MASK, + .sram_pdn_mask = DISP_SRAM_PDN_MASK, + .sram_ack_mask = DISP_SRAM_ACK_MASK, + }, +}; + +static const struct power_domain_data audio[] = { + { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = AUDIO_PWR_STA_MASK, + .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, + .sram_ack_mask = AUDIO_SRAM_ACK_MASK, + }, +}; + #endif /* SOC_MEDIATEK_MT8192_SPM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c3d19f1e9a4e516d674d68989ad509f37e5b593 Gerrit-Change-Number: 52881 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-Attention: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Fix the FSP-T position
by Arthur Heymans (Code Review) 04 May '21

04 May '21

Attention is currently required from: Michał Żygowski, Paul Menzel, Andrey Petrov, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52850 ) Change subject: drivers/intel/fsp2_0: Fix the FSP-T position ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52850/comment/11083614_f8db81c7 PS2, Line 7: FSP_T > FSP-T as below? Done https://review.coreboot.org/c/coreboot/+/52850/comment/144e514b_d3941188 PS2, Line 10: > nit: "but"? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Gerrit-Change-Number: 52850 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 May 2021 08:51:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pc80/rtc/option.c: Constrain API to integer values
by Patrick Rudolph (Code Review) 04 May '21

04 May '21

Attention is currently required from: Angel Pons, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52637 ) Change subject: drivers/pc80/rtc/option.c: Constrain API to integer values ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5 Gerrit-Change-Number: 52637 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 04 May 2021 08:44:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Fix the FSP-T position
by Arthur Heymans (Code Review) 04 May '21

04 May '21

Attention is currently required from: Michał Żygowski, Paul Menzel, Arthur Heymans, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Patrick Georgi, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52850 to look at the new patch set (#4). Change subject: drivers/intel/fsp2_0: Fix the FSP-T position ...................................................................... drivers/intel/fsp2_0: Fix the FSP-T position The only use case for FSP-T in coreboot is for 'Intel Bootguard' support at the moment. Bootguard can do verification FSP-T but there is no verification on whether the FSP found by walkcbfs_asm is the one actually verified as an IBB by Bootguard. A fixed pointer needs to be used. TESTED on OCP/Deltalake, still boots. Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 3 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/52850/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Gerrit-Change-Number: 52850 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src: Retype option API to use unsigned integers
by Patrick Rudolph (Code Review) 04 May '21

04 May '21

Attention is currently required from: Felix Singer, Nico Huber, Damien Zammit, Tristan Corrick, Angel Pons, Alexander Couzens, Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52672 ) Change subject: src: Retype option API to use unsigned integers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Gerrit-Change-Number: 52672 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Damien Zammit Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 May 2021 08:43:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT
by Kane Chen (Code Review) 04 May '21

04 May '21

Attention is currently required from: Karthik Ramasubramanian. Hello build bot (Jenkins), Kane Chen, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52874 to look at the new patch set (#5). Change subject: soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT ...................................................................... soc/intel/{adl, tgl, jsl}: Enable power button smi after BS_CHIPS_EXIT On tgl, we noticed system hang if a shutdown is triggered before fsps. The dut is unable to shutdown properly due to tcss is stuck before tcss_init in fsps. This change enable power button smi on jsl, tgl, adl after fsps. it can also prevent a shutdown failure due to lack of fsps init on certain ip. BUG=b:186194102, b:186815114 Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pmc.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/pmc.c 6 files changed, 35 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/52874/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Gerrit-Change-Number: 52874 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/vilboz: Disable HDMI 2.0 for Vilboz
by Patrick Georgi (Code Review) 04 May '21

04 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52724 ) Change subject: mb/google/zork/vilboz: Disable HDMI 2.0 for Vilboz ...................................................................... mb/google/zork/vilboz: Disable HDMI 2.0 for Vilboz Disable HDMI 2.0 for Vilboz and then support display resolution 4K 30Hz BUG=b:179170193 BRANCH=firmware-zork-13434.B TEST=verified that the resolution of the display is 4K 30Hz Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52724 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Patrick Huang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index fac4c7f..43a64b0d 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -42,6 +42,11 @@ register "pwrdown_bloff_to_varybloff" = "5" register "min_allowed_bl_level" = "0" + # Set HDMI 2.0 disable function + # bit0~3: disable HDMI 2.0 DDI0~3 + # disable DDI1 + register "hdmi2_disable" = "2" + # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440 Gerrit-Change-Number: 52724 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit May 2021