coreboot-gerrit May 2021

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Change in coreboot[master]: mainboard/google/brya: Add S3/S0ix wake events AC connect/disconnect
by Werner Zeh (Code Review) 28 May '21

28 May '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54855 ) Change subject: mainboard/google/brya: Add S3/S0ix wake events AC connect/disconnect ...................................................................... mainboard/google/brya: Add S3/S0ix wake events AC connect/disconnect Enabling AC connect/disconnect wake events in brya to meet Chrome OS wake requirements. These changes are similar to Volteer and Shadowmountain. BUG=none BRANCH=None TEST=manual tested DUT wakes for AC connect/disconnect in S0ix Change-Id: I14b3efd429e3aa701af534f150baf35fcdeb9f35 Signed-off-by: madhusudanarao amara <madhusudanarao.amara(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54855 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Sooraj Govindan <sooraj.govindan(a)intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h 1 file changed, 7 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Sooraj Govindan: Looks good to me, but someone else must approve Madhusudanarao Amara: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h index d01b450..34297bf 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h @@ -33,13 +33,16 @@ /* * EC can wake from S3/S0ix with: * 1. Lid open - * 2. Power button - * 3. Key press - * 4. Mode change + * 2. AC Connect/Disconnect + * 3. Power button + * 4. Key press + * 5. Mode change */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) /* Log EC wake events plus EC shutdown events */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14b3efd429e3aa701af534f150baf35fcdeb9f35 Gerrit-Change-Number: 54855 Gerrit-PatchSet: 6 Gerrit-Owner: Madhusudanarao Amara <madhusudanarao.amara(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Madhusudanarao Amara <madhusudanarao.amara(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.com> Gerrit-Reviewer: Sooraj Govindan <sooraj.govindan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/wilco: Extend description of `EC_GOOGLE_WILCO`
by Werner Zeh (Code Review) 28 May '21

28 May '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54929 ) Change subject: ec/google/wilco: Extend description of `EC_GOOGLE_WILCO` ...................................................................... ec/google/wilco: Extend description of `EC_GOOGLE_WILCO` Change-Id: Ia278b538a8904651d16c37d095972fa78e264288 Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/7S5O… Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54929 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/wilco/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index ee7b556..f97fa26d 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -7,6 +7,13 @@ help Google Wilco Embedded Controller interface. + Note, the Wilco EC firmware is a modified version of Dell's + typical Latitude EC firmware, that implements a custom mailbox + protocol similar to the one used in the Chromium EC. + + This particular EC firmware is not open source, just the + host-side interfaces (kernel and firmware drivers) are. + if EC_GOOGLE_WILCO config EC_BASE_ACPI_DATA -- To view, visit https://review.coreboot.org/c/coreboot/+/54929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia278b538a8904651d16c37d095972fa78e264288 Gerrit-Change-Number: 54929 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by EricR Lai (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Amanda Hwang. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55000 ) Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55000/comment/0e6e2b3e_03896c3a PS1, Line 9: Correct the attributes ranksPerChannel as 2 for LP4x global config. > > I assume not, it only use diesperpakcage. […] oh, it will change this value encodeModuleOrganization. never mind... you can ignore my comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 May 2021 04:45:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/ehlcrb: Upload EHL CRB GPIO configs
by Werner Zeh (Code Review) 28 May '21

28 May '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54891 ) Change subject: mb/intel/ehlcrb: Upload EHL CRB GPIO configs ...................................................................... mb/intel/ehlcrb: Upload EHL CRB GPIO configs Initial upload of the GPIO configs for EHL CRB. This CL also includes the UART GPIO configs in early GPIO table. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c 1 file changed, 256 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c index 003a6a5..9d17c80 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -5,12 +5,266 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configurations */ +/*BT_RF_KILL_N*/ +PAD_CFG_GPO(GPP_E11, 1, DEEP), + +/*WIFI_RF_KILL_N*/ +PAD_CFG_GPO(GPP_E10, 1, DEEP), + +/*M.2_WLAN_PERST_N*/ +PAD_CFG_GPO(GPD7, 1, PLTRST), + +/*M.2_WLAN_SLP*/ +PAD_CFG_GPO(GPD9, 1, PLTRST), + +/*WIFI_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_F4, UP_5K, DEEP, LEVEL, INVERT), + +/*UART_BT_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_F20, NONE, DEEP, LEVEL, INVERT), + +/*ONBOARD_X4_PCIE_SLOT1_RESET_N*/ +PAD_CFG_GPO(GPD11, 1, PLTRST), + +/*ONBOARD_X4_PCIE_SLOT1_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + +/*M.2_WWAN_PWR_EN*/ +PAD_CFG_GPO(GPP_F21, 1, PLTRST), + +/*M.2_WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 1, PLTRST), + +/*M.2_WWAN_PE_RST_N*/ +PAD_CFG_GPO(GPP_B14, 1, PLTRST), + +/*M.2_WWAN_PE_WAKE_N*/ +PAD_CFG_GPO(GPP_B17, 1, PLTRST), + +/*M.2_WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 1, PLTRST), + +/*M.2_SSD_SATA_DEVSLP_1*/ +PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + +/*BC_PROCHOT_N*/ +PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), + +/*FPS_RST_N*/ +PAD_CFG_GPO(GPP_V14, 1, PLTRST), + +/*FPS_INT*/ +PAD_CFG_GPI_APIC(GPP_V15, NONE, PLTRST, LEVEL, NONE), + +/*CODEC_INT_N*/ +PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + +/*TCH_PNL_PWR_EN*/ +PAD_CFG_GPO(GPP_B16, 1, PLTRST), + +/*THC0_SPI1_INT_N*/ +PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, INVERT), + +/*SPI_TPM_INT_N*/ +PAD_CFG_GPI_APIC(GPP_G19, NONE, DEEP, LEVEL, NONE), + +/*EMMC_CMD*/ +PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), + +/*EMMC_DATA0*/ +PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), + +/*EMMC_DATA1*/ +PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), + +/*EMMC_DATA2*/ +PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), + +/*EMMC_DATA3*/ +PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), + +/*EMMC_DATA4*/ +PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), + +/*EMMC_DATA5*/ +PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), + +/*EMMC_DATA6*/ +PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), + +/*EMMC_DATA7*/ +PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), + +/*EMMC_RCLK*/ +PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), + +/*EMMC_CLK*/ +PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), + +/*EMMC_RESET*/ +PAD_CFG_NF(GPP_V11, UP_20K, DEEP, NF1), + +/*ACPRESENT*/ +PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), + +/*RGMII0_MDC*/ +PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + +/*RGMII0_MDIO*/ +PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + +/*RGMII0_INT*/ +PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + +/*RGMII0_RESETB*/ +PAD_CFG_GPO(GPP_T5, 1, DEEP), + +/*RGMII0_AUXTS*/ +PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + +/*RGMII1_MDC*/ +PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + +/*RGMII1_MDIO*/ +PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + +/*RGMII1_INT*/ +PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), + +/*RGMII1_RESETB*/ +PAD_CFG_GPO(GPP_H1, 1, DEEP), + +/*RGMII1_AUXTS*/ +PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + +/*RGMII2_MDC*/ +PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + +/*RGMII2_MDIO*/ +PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + +/*RGMII2_INT*/ +PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1), + +/*RGMII2_RESETB*/ +PAD_CFG_GPO(GPP_U1, 1, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configurations */ +/* UART1 RX */ +PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), + +/* UART1 TX */ +PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), + +/* UART2 RX */ +PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), + +/* UART2 TX */ +PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), + +/*WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 1, PLTRST), + +/*WWAN_PWREN*/ +PAD_CFG_GPO(GPP_F21, 1, PLTRST), + +/*WWAN_PERST_N*/ +PAD_CFG_GPO(GPP_B14, 0, PLTRST), + +/*WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 0, PLTRST), + +/* LAN_WAKEB*/ +PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, EDGE_SINGLE, INVERT), + +/*WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 0, PWROK), + +/*WWAN_PERST_N*/ +PAD_CFG_GPO(GPP_B14, 0, PWROK), + +/*WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 0, PWROK), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/54891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e Gerrit-Change-Number: 54891 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by Furquan Shaikh (Code Review) 28 May '21

28 May '21

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55000 ) Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55000/comment/33668fd2_533b5627 PS1, Line 9: Correct the attributes ranksPerChannel as 2 for LP4x global config. > I assume not, it only use diesperpakcage. Sorry, I did not understand your comment Eric. -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 May 2021 04:21:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by Amanda Hwang (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Amanda Hwang. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55000 to look at the new patch set (#5). Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/55000/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by Amanda Hwang (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Amanda Hwang. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55000 to look at the new patch set (#4). Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/55000/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by Amanda Hwang (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Amanda Hwang. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55000 to look at the new patch set (#3). Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/55000/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 3 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by Amanda Hwang (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Amanda Hwang. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55000 to look at the new patch set (#2). Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/55000/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS
by Name of user not set (Code Review) 28 May '21

28 May '21

Name of user not set #1003548 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55005 ) Change subject: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/55005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d41c73ffe8377c6014abe77a8921497a41bcb9 Gerrit-Change-Number: 55005 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1003548 Gerrit-Comment-Date: Fri, 28 May 2021 00:56:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021