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Hello build bot (Jenkins), Henry Sun, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52565
to look at the new patch set (#3).
Change subject: mb/google/dedede/var/galith: Support Wifi SAR for DVT phase
......................................................................
mb/google/dedede/var/galith: Support Wifi SAR for DVT phase
Because galith/gallop both non-suport tablet mode,
remove un-use fw_config conditional.
BUG=b:176206495
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: Ic9bb76c207ef033f81ecdd57849535b8ac8d13ae
---
M src/mainboard/google/dedede/variants/galtic/variant.c
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/52565/3
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Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52565 )
Change subject: mb/google/dedede/var/galith: Support Wifi SAR for DVT phase
......................................................................
Patch Set 2: Code-Review+1
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51631 )
Change subject: [WIP] soc/intel/braswell: Use SOC_INTEL_COMMON_BLOCK_I2C
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/braswell/acpi/lpss.asl:
https://review.coreboot.org/c/coreboot/+/51631/comment/66a7c8ac_fa5d714d
PS1, Line 104: /* Standard Mode: HCNT, LCNT, SDA Hold Time */
: Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C1_DATA_HOLD_TIME })
:
: /* Fast Mode: HCNT, LCNT, SDA Hold Time */
: Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C1_DATA_HOLD_TIME })
> I have no clue weather there is a dependency to this inside the OS. […]
Yes, someone with hardware access should take action to make this move forwards.
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Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
I think it's a little strange to set i2c speed twice, but the designware driver is built that way.
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Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
The .rise_time_ns approach might be the recommended and more recent one to use.
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Change subject: [WIP] soc/intel/braswell: Use SOC_INTEL_COMMON_BLOCK_I2C
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/braswell/acpi/lpss.asl:
https://review.coreboot.org/c/coreboot/+/51631/comment/71ff3e43_1cda1286
PS1, Line 104: /* Standard Mode: HCNT, LCNT, SDA Hold Time */
: Name (SSCN, Package () { 0x200, 0x200, BOARD_I2C1_DATA_HOLD_TIME })
:
: /* Fast Mode: HCNT, LCNT, SDA Hold Time */
: Name (FMCN, Package () { 0x55, 0x99, BOARD_I2C1_DATA_HOLD_TIME })
I have no clue weather there is a dependency to this inside the OS. I understand your motivation for this change but I guess someone with access to said boards should have a look and provide matching values instead of deleting them completely.
File src/soc/intel/braswell/chip.c:
https://review.coreboot.org/c/coreboot/+/51631/comment/b0c499d4_8e15deb3
PS1, Line 144: i2c_frequency(config, 0);
The API does not match here (additional second parameter ), I guess hence the Jenkins-error?
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