coreboot-gerrit March 2021

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Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Mariusz Szafrański (Code Review) 02 Mar '21

02 Mar '21

Mariusz Szafrański has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... util/sconfig: Fix for multidomain support sconfig/devicetree.cb Fixes sconfig related build errors while there exists DEV.FUNC number shared by two devices from different domains (root buses) i.e. device domain 0 on device pci 00.0 on end ....... end device domain 1 on device pci 00.0 on end ....... end Two domains (each with it`s own root PCI bus) and device with 00.0 exists on both buses. Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> --- M util/sconfig/main.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/51180/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 91407bc..5df8b94 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1219,10 +1219,10 @@ /* Only devices on root bus here. */ if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { - fprintf(head, "extern DEVTREE_CONST struct device *const __pci_0_%02x_%d;\n", - ptr->path_a, ptr->path_b); - fprintf(fil, "DEVTREE_CONST struct device *const __pci_0_%02x_%d = &%s;\n", - ptr->path_a, ptr->path_b, ptr->name); + fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_%d_%02x_%d;\n", + ptr->parent->dev->path_a, ptr->path_a, ptr->path_b); + fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_%d_%02x_%d = &%s;\n", + ptr->parent->dev->path_a, ptr->path_a, ptr->path_b, ptr->name); if (chip_ins->chip->chiph_exists) { fprintf(head, "extern DEVTREE_CONST void *const __pci_0_%02x_%d_config;\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 1 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: The current f1 to f12 as primary just enables FN Lock and causes a li...
by Forkoz (Code Review) 02 Mar '21

02 Mar '21

Forkoz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51179 ) Change subject: The current f1 to f12 as primary just enables FN Lock and causes a light to enable on the keyboard of the T440P. Newer machine firmware has the option to invert FN Lock so that the unlocked state has the light on and locked has it off. This way you have no light and can use the F keys instead of hotkeys unless you hold FN or enable FN lock. ...................................................................... The current f1 to f12 as primary just enables FN Lock and causes a light to enable on the keyboard of the T440P. Newer machine firmware has the option to invert FN Lock so that the unlocked state has the light on and locked has it off. This way you have no light and can use the F keys instead of hotkeys unless you hold FN or enable FN lock. Obviously now we don't want FN lock on by default. This was tested on both the T440P and X250 so should be present in all thinkpads with a FN light that had the option in the bios. Change-Id: Ic3f03a9fbd7e16d6c30828a66502d2b72f499dfe --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/h8.c M src/mainboard/lenovo/t440p/cmos.default M src/mainboard/lenovo/t440p/cmos.layout 4 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/51179/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index 2ea4faa9..16fe156 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -44,6 +44,10 @@ bool default n +config H8_SWAP_FN_LOCK + bool + default n + config THINKPADEC_HKEY_EISAID string default "IBM0068" diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 093a639..310b4e0 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -76,9 +76,18 @@ static void f1_to_f12_as_primary(int on) { if (on) - ec_set_bit(0x3b, 3); + ec_set_bit(0x3b, 3); // Enable FN Lock else - ec_clr_bit(0x3b, 3); + ec_clr_bit(0x3b, 3); //Undo +} + +static void fn_lock_swap(int on) +{ + if (on) + ec_clr_bit(0x09, 3); // T440p/X250 invert FN Lock + else + ec_set_bit(0x09, 3); // Undo + } static void h8_log_ec_version(void) @@ -337,6 +346,12 @@ f1_to_f12_as_primary(val); } + if (CONFIG(H8_SWAP_FN_LOCK)) { + if (get_option(&val, "fn_lock_swap") != CB_SUCCESS) + val = 1; + fn_lock_swap(val); + } + if (get_option(&val, "first_battery") != CB_SUCCESS) val = PRIMARY_BATTERY; h8_charge_priority(val); diff --git a/src/mainboard/lenovo/t440p/cmos.default b/src/mainboard/lenovo/t440p/cmos.default index bb8626d..b5ae6e5 100644 --- a/src/mainboard/lenovo/t440p/cmos.default +++ b/src/mainboard/lenovo/t440p/cmos.default @@ -6,7 +6,8 @@ first_battery=Primary wlan=Enable fn_ctrl_swap=Disable -f1_to_f12_as_primary=Enable +f1_to_f12_as_primary=Disable +fn_lock_swap=Enable sticky_fn=Disable trackpoint=Enable backlight=Keyboard diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 464d242..e48d93a 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -30,6 +30,7 @@ 419 2 e 13 usb_always_on 422 2 e 10 backlight 424 1 e 1 f1_to_f12_as_primary +425 1 e 1 fn_lock_swap # coreboot config options: northbridge 435 1 e 1 enable_dual_graphics -- To view, visit https://review.coreboot.org/c/coreboot/+/51179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f03a9fbd7e16d6c30828a66502d2b72f499dfe Gerrit-Change-Number: 51179 Gerrit-PatchSet: 1 Gerrit-Owner: Forkoz <Crabstorage(a)getbackinthe.kitchen> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Add log_level that can be overridden for SMM log level
by Johnny Lin (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Marc Jones, Patrick Rudolph, Jonathan Zhang, Rocky Phagura, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49460 ) Change subject: cpu/x86/smm: Add log_level that can be overridden for SMM log level ...................................................................... Patch Set 4: (2 comments) Patchset: PS3: > https://review.coreboot. […] Thanks for your work, I rebase on top of your change CB:50767 and add a log_level variable for this purpose. File src/cpu/x86/smm/smm_module_loaderv2.c: https://review.coreboot.org/c/coreboot/+/49460/comment/ff298f69_00decaef PS2, Line 639: params->handler_arg = (void *) &smm_param_loglevel; > A very ugly solution: use GNVS. Implement on top of CB:50767 -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 14:02:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marc Jones <marc(a)marcjonesconsulting.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Add log_level that can be overridden for SMM log level
by Johnny Lin (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Marc Jones, Patrick Rudolph, Jonathan Zhang, Johnny Lin, Rocky Phagura, Jingle Hsu, Morgan Jang. Hello build bot (Jenkins), Marc Jones, Patrick Rudolph, Jonathan Zhang, Rocky Phagura, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49460 to look at the new patch set (#4). Change subject: cpu/x86/smm: Add log_level that can be overridden for SMM log level ...................................................................... cpu/x86/smm: Add log_level that can be overridden for SMM log level When CONSOLE_OVERRIDE_LOGLEVEL is selected, ramstage can pass SMM console log level via this variable and later be referenced in SMM get_console_loglevel() override function. The purpose is that getting the log level may spend too much time such as searching for the key-value from flash VPD, which is not ideal for SMM. Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_module_loaderv2.c M src/include/console/console.h M src/include/cpu/x86/smm.h 5 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/49460/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: fix BT enumeration issue
by Aamir Bohra (Code Review) 02 Mar '21

02 Mar '21

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51178 ) Change subject: mb/google/brya: fix BT enumeration issue ...................................................................... mb/google/brya: fix BT enumeration issue Current implementation exposes GPP_F4 cnvi reset pin as reset gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven by SoC. It should not be driven by driver. Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/51178/1 diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 030d19e..86d022d 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -273,7 +273,7 @@ register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F4)" + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port10 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/51178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Gerrit-Change-Number: 51178 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/drivers/i2c/rx6110sa: Add official ACPI ID
by Werner Zeh (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Andy Shevchenko, Paul Menzel, Johannes Hahn. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51176 ) Change subject: src/drivers/i2c/rx6110sa: Add official ACPI ID ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Thank you very much for the effort (I wish all hardware vendors would do like this)! Your objection was justified from the first minute. Thank you for bringing this up which made our code better. -- To view, visit https://review.coreboot.org/c/coreboot/+/51176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45838162f014a760520692c6dcaae329ad98547d Gerrit-Change-Number: 51176 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 12:51:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/i2c/rx6110sa: Add official ACPI ID
by Andy Shevchenko (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Paul Menzel, Werner Zeh, Johannes Hahn. Andy Shevchenko has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51176 ) Change subject: src/drivers/i2c/rx6110sa: Add official ACPI ID ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Thank you very much for the effort (I wish all hardware vendors would do like this)! -- To view, visit https://review.coreboot.org/c/coreboot/+/51176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45838162f014a760520692c6dcaae329ad98547d Gerrit-Change-Number: 51176 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 12:31:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/i2c/rx6110sa: Add official ACPI ID
by Werner Zeh (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51176 to look at the new patch set (#2). Change subject: src/drivers/i2c/rx6110sa: Add official ACPI ID ...................................................................... src/drivers/i2c/rx6110sa: Add official ACPI ID In commit 2609eaaa8f (src/drivers/i2c/rx6110sa: Omit _HID temporarily) the randomly assigned and therefore wrong ACPI ID for RTC RX6110SA was removed. In the meantime Seiko-Epson did a great job and registered an official vendor ID in the ACPI database [1]. Further on, Seiko-Epson has now assigned the unique Product Identifier for the RX6110SA, which is '6110'. The assignment of the Product Identifier is controlled by the vendor and there is no official database where this ID is stored in. It is up to the vendor to make sure that this ID stays unique. This patch adds this new vendor and product ID to the driver. Together with a pending Linux patch this RTC is now useable as ACPI device in Linux. [1] https://uefi.org/ACPI_ID_List?search=SECC Change-Id: I45838162f014a760520692c6dcaae329ad98547d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/rx6110sa/rx6110sa.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/51176/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45838162f014a760520692c6dcaae329ad98547d Gerrit-Change-Number: 51176 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lenovo/x200: Fix docking events
by Patrick Georgi (Code Review) 02 Mar '21

02 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51118 ) Change subject: mb/lenovo/x200: Fix docking events ...................................................................... mb/lenovo/x200: Fix docking events Even though `device` entries are children of `chip` entries in the devicetree source format, the chips in the translated C structures are only hooked up to device nodes. Hence, to configure a chip in a device- or overridetree, it always needs a `device` below it. This should fix docking events for the X200 ThinkPad. Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Found-by: Kevin Keijzer <kevin(a)quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51118 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kevin Keijzer Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/variants/x200/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved Kevin Keijzer: Looks good to me, but someone else must approve diff --git a/src/mainboard/lenovo/x200/variants/x200/overridetree.cb b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb index dd08f1f..51beecc 100644 --- a/src/mainboard/lenovo/x200/variants/x200/overridetree.cb +++ b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb @@ -16,6 +16,7 @@ device pci 1f.0 on # LPC bridge chip ec/lenovo/pmh7 + device pnp ff.1 on end # dummy register "dock_event_enable" = "0x01" end chip superio/nsc/pc87382 -- To view, visit https://review.coreboot.org/c/coreboot/+/51118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067 Gerrit-Change-Number: 51118 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Kevin Keijzer Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K
by Hung-Te Lin (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51174 ) Change subject: soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8192/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/51174/comment/82da3671_bb9499a5 PS1, Line 51: 128K > For full calibration, the romstage log can be as large as 430K, which is larger than the default cbm […] Do you mean config CONSOLE_CBMEM_BUFFER_SIZE ? We can definitely increase that as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/51174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896884d298e197149f75865e9d00579124a34404 Gerrit-Change-Number: 51174 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 12:09:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2021