coreboot-gerrit March 2021

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Change in coreboot[master]: mb/google/brya: Temporarily disable recovery MRC cache
by Tim Wawrzynczak (Code Review) 04 Mar '21

04 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51262 ) Change subject: mb/google/brya: Temporarily disable recovery MRC cache ...................................................................... mb/google/brya: Temporarily disable recovery MRC cache There is a bug yet to be root-caused that, when a board is booted for the first time with recovery MRC cache enabled, coreboot will fail to lock the recovery MRC hash space in the TPM and will reboot, whereas it should instead boot to recovery (which will create the space in the TPM) and any subsequent boots will be fine. However, this first boot then turns into a boot-loop until the user manually enters recovery mode. Until this bug is fixed, disable the recovery MRC cache. BUG=b:181678769 Change-Id: Ia2189066e9a089293edada6403c7defe60f3aa33 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/51262/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b3006cb..e35559a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -29,7 +29,6 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH config DEVICETREE -- To view, visit https://review.coreboot.org/c/coreboot/+/51262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2189066e9a089293edada6403c7defe60f3aa33 Gerrit-Change-Number: 51262 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/adl, mb/google/brya: Add IPU to devicetree
by Tim Wawrzynczak (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51261 ) Change subject: soc/intel/adl, mb/google/brya: Add IPU to devicetree ...................................................................... soc/intel/adl, mb/google/brya: Add IPU to devicetree Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chipset.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/51261/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index d82a9eb..a0941a7 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -91,6 +91,7 @@ device domain 0 on device ref igpu on end device ref dtt on end + device ref ipu on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end device ref tbt_pcie_rp2 on end diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 173d3e0..cd9ebf9 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -5,6 +5,7 @@ device pci 01.0 alias pcie5 off end device pci 02.0 alias igpu off end device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end device pci 06.0 alias pcie4_0 off end device pci 06.2 alias pcie4_1 off end device pci 07.0 alias tbt_pcie_rp0 off -- To view, visit https://review.coreboot.org/c/coreboot/+/51261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Gerrit-Change-Number: 51261 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: brya0: Add ACPI support for Type-C ports
by Tim Wawrzynczak (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Tim Wawrzynczak, Aamir Bohra, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Aamir Bohra, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51258 to look at the new patch set (#2). Change subject: mb/google/brya: brya0: Add ACPI support for Type-C ports ...................................................................... mb/google/brya: brya0: Add ACPI support for Type-C ports BUG=b:181160586, b:181843816 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/dsdt.asl M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/51258/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 Gerrit-Change-Number: 51258 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add IPU ASL to DSDT
by Tim Wawrzynczak (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Furquan Shaikh, Aamir Bohra, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51259 ) Change subject: mb/google/brya: Add IPU ASL to DSDT ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51259/comment/589f55c2_ac581dfa PS1, Line 7: IPU > Don't you also need some changes in devicetree/overridetree? We do not have a PCI device for IPU in devicetree for ADL currently, but it was found during PCI enumeration and the OS is also enumerating it. Also noticed the COMMON_IPU driver has the ADL PCI ID in it. I'll add onto this to make the support explicit. -- To view, visit https://review.coreboot.org/c/coreboot/+/51259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4 Gerrit-Change-Number: 51259 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Mar 2021 17:42:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/soc/intel: Add common code 2.0 romstage design document
by Bernardo Perez Priego (Code Review) 04 Mar '21

04 Mar '21

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51260 ) Change subject: Documentation/soc/intel: Add common code 2.0 romstage design document ...................................................................... Documentation/soc/intel: Add common code 2.0 romstage design document Add common code 2.0 romstage design document for Intel SOC's. Documented items: *Introduction *Redundant code identified *Proposed solution *Conclusion Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I6b4b467149bbfac3f736be544bd9b754c96f64f9 --- A Documentation/soc/intel/code_development_model/coreboot_common_code_2_0_romstage.md 1 file changed, 143 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/51260/1 diff --git a/Documentation/soc/intel/code_development_model/coreboot_common_code_2_0_romstage.md b/Documentation/soc/intel/code_development_model/coreboot_common_code_2_0_romstage.md new file mode 100644 index 0000000..daf9a66 --- /dev/null +++ b/Documentation/soc/intel/code_development_model/coreboot_common_code_2_0_romstage.md @@ -0,0 +1,143 @@ +# Intel common code 2.0 romstage strategy + +## Introduction + +This document has the intention of describing the efforts to reduce the amount +of code duplicated in Romstage across multiple Intel SOC's. This reduction is +achieved by identifying sections of code that are redundant, to encapsulate +this code in such way that common code can be reused and any SOC specific +features can be added easily. + +The main purpose of Romstage is to configure DDR controller to access main +memory. This is a complex process that is done by Intel FSP. During its +execution, Romstage will locate, load, configure and execute FSP module in +charge of memory initialization. + +## Redundant code identified + +#### Romstage entry +``mainboard_romstage_entry`` function is our first example, this is redefined +within every Intel SOC folder, please note that each instance of this function +has similar structure. + +### Is S3 awake +Composed by functions ``pmc_get_power_state`` and ``pmc_fill_power_state``, +this routine is used to determine if system is coming from warm boot (S3), +this information is required by memory initialization and afterwards during +romstage execution. + +#### FSP Memory Initialization +FSP memory initialization is invoked using API ``fsp_memory_init``, this function +will locate, load and execute memory initialization module. Prior FSP module +execution, ``platform_fsp_memory_init_params_cb`` will be called. Every SOC is +responsible for defining this function, one of its parameters is a pointer to +UPD structure. Implementation must include populating UPD structure with desired +memory configuration. + +### DIMM information storage +After memory is initialized, SOC will export memory parameters using SMBIOS +interface, various parameters are obtained from HOB buffers after cold boot. +See function ``save_dimm_info``. + +### To find definitions of above mentioned, please refer to following files: +- **CNL** - src/soc/intel/cannonlake/romstage/romstage.c +- **SKL** - src/soc/intel/skylake/romstage/romstage.c +- **TGL** - src/soc/intel/tigerlake/romstage/romstage.c + +#### PCH Initialization +Another routine that share this similarities is pch intialization, this can be +marked as common code, please refer to: +- **TGL PCH** - src/soc/intel/tigerlake/romstage/pch.c +- **SKL PCH** - src/soc/intel/skylake/romstage/pch.c +- **CNL PCH** - src/soc/intel/cannonlake/romstage/pch.c + +## Proposed solution +From above observations we could proceed to have a generic execution flow and +a common romstage entry for all SOC’s. Execution flow can be defined in +following four phases: + +1 Initialization +- SOC +- PCH +- CPU + +2 FSP memory initialization configuration +- Set SOC parameters +- Set Mainboard parameters + +3 FSP memory initialization execution + +4 FSP post memory initialization +- SOC +- Mainboard + +Note that execution flow is fixed. However, each subphase implementation is +declared as ``__weak``, this way we can redefine, stub or extended common code +depending on platform requirements. + +This is how common code inside some rewritable functions are declared: +``` +void romstage_cmn_xxxxxxx(void) +``` +user is free to call this function on its subphase implementation accordingly. + +### Execution Flow +Main entry function: +``` +void mainboard_romstage_entry(void) +{ + bool s3wake = romstage_is_s3wake(); + romstage_init(); + fsp_memory_init(s3wake); + romstage_post_mem_init(); +} +``` + +Initialization phase include three functions: +``` +static void romstage_init(void) +{ + romstage_soc_init(); + romstage_pch_init(); + romstage_cpu_init(); +} + +void __weak romstage_soc_init(void) + +void __weak romstage_pch_init(void) + +void __weak romstage_cpu_init(void) +``` + +Same way with fsp memory intitialization phase: +``` +static void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + romstage_soc_mem_init_params(mupd, version); + + romstage_mb_mem_init_params(mupd); +} + +void __weak romstage_soc_post_mem_init(void) + +void __weak romstage_mb_post_mem_init(void) +``` + +Finally post memory initialization phase: +``` +static void romstage_post_mem_init(void) +{ + romstage_soc_post_mem_init(); + romstage_mb_post_mem_init(); +} + +void __weak romstage_soc_post_mem_init(void) + +void __weak romstage_mb_post_mem_init(void) +``` + +## Conclusion +Reducing code duplicates facilitates project support, new fixes can be ported to +other SOC's that this may apply with minimal effort. +Having a uniform execution flow will not only make code easier to understand but +also allow new SOC's to quickly start development. -- To view, visit https://review.coreboot.org/c/coreboot/+/51260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b4b467149bbfac3f736be544bd9b754c96f64f9 Gerrit-Change-Number: 51260 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add IPU ASL to DSDT
by Furquan Shaikh (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Tim Wawrzynczak, Aamir Bohra, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51259 ) Change subject: mb/google/brya: Add IPU ASL to DSDT ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51259/comment/ed986b94_a7bbd697 PS1, Line 7: IPU Don't you also need some changes in devicetree/overridetree? -- To view, visit https://review.coreboot.org/c/coreboot/+/51259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4 Gerrit-Change-Number: 51259 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Mar 2021 17:30:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add IPU ASL to DSDT
by Furquan Shaikh (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Tim Wawrzynczak, Aamir Bohra, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51259 ) Change subject: mb/google/brya: Add IPU ASL to DSDT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4 Gerrit-Change-Number: 51259 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Mar 2021 17:29:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: brya0: Add ACPI support for Type-C ports
by Furquan Shaikh (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Tim Wawrzynczak, Aamir Bohra, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51258 ) Change subject: mb/google/brya: brya0: Add ACPI support for Type-C ports ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51258/comment/5bfe2529_5d919e0c PS1, Line 8: BUG=b:? File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/51258/comment/53813830_ceef9cd8 PS1, Line 214: # SBU & HSL follow CC Why is this comment specific to port0? -- To view, visit https://review.coreboot.org/c/coreboot/+/51258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 Gerrit-Change-Number: 51258 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Mar 2021 17:26:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
by Brandon Breitenstein (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Chiranjeevi Rapolu, Tim Wawrzynczak. Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51194 ) Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/51194/comment/7b4351b3_47f5a777 PS9, Line 113: usb3_port > Brandon, I assume 1-based numbering is taken care here. IOM is expecting the 1 based numbering to my knowledge -- To view, visit https://review.coreboot.org/c/coreboot/+/51194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Gerrit-Change-Number: 51194 Gerrit-PatchSet: 9 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Mar 2021 17:25:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: brya0: Add ACPI support for Type-C ports
by Tim Wawrzynczak (Code Review) 04 Mar '21

04 Mar '21

Attention is currently required from: Furquan Shaikh, Aamir Bohra, EricR Lai. Tim Wawrzynczak has removed Aamir Bohra from this change. ( https://review.coreboot.org/c/coreboot/+/51258 ) Change subject: mb/google/brya: brya0: Add ACPI support for Type-C ports ...................................................................... Removed reviewer Aamir Bohra. -- To view, visit https://review.coreboot.org/c/coreboot/+/51258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 Gerrit-Change-Number: 51258 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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coreboot-gerrit March 2021