Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51261 )
Change subject: soc/intel/adl, mb/google/brya: Add IPU to devicetree ......................................................................
soc/intel/adl, mb/google/brya: Add IPU to devicetree
Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chipset.cb 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/51261/1
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index d82a9eb..a0941a7 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -91,6 +91,7 @@ device domain 0 on device ref igpu on end device ref dtt on end + device ref ipu on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end device ref tbt_pcie_rp2 on end diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 173d3e0..cd9ebf9 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -5,6 +5,7 @@ device pci 01.0 alias pcie5 off end device pci 02.0 alias igpu off end device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end device pci 06.0 alias pcie4_0 off end device pci 06.2 alias pcie4_1 off end device pci 07.0 alias tbt_pcie_rp0 off