coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design This change uses the following information to determine the appropriate S0ix states to enable as per PDG document: 607872 for TGL UP3 UP Rev2p2 (section 10.13): 1. SoC - UP3 v/s UP4 2. H/W design - external phy gating, external clk gating, external bypass 3. Devices enabled at runtime - CNVi, ISH In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document. Deepest state expected on tigerlake up3 based platforms is S0i3.2. BUG=b:177821896 TEST=Build coreboot for volteer. Verify that deepest S0ix substate that is enabled is S0i3.1 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766 Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 77 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Wonkyu Kim: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index edc7160..cccf804 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -499,6 +499,30 @@ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; + + /* + * External Clock Gate + * true = Mainboard design uses external clock gating + * false = Mainboard design does not use external clock gating + * + */ + bool external_clk_gated; + + /* + * External PHY Gate + * true = Mainboard design uses external phy gating + * false = Mainboard design does not use external phy gating + * + */ + bool external_phy_gated; + + /* + * External Bypass Enable + * true = Mainboard design uses external bypass rail + * false = Mainboard design does not use external bypass rail + * + */ + bool external_bypass; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index c0d712c..90d6805 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -3,7 +3,10 @@ #include <assert.h> #include <console/console.h> #include <device/device.h> +#include <arch/pci_io_cfg.h> +#include <device/pci_ops.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <fsp/api.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> @@ -50,6 +53,55 @@ return ctl - 1; } +/* Function returns true if the platform is TGL-UP3 */ +static bool platform_is_up3(void) +{ + const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + u32 cpu_id = cpu_get_cpuid(); + uint16_t mchid = pci_read_config16(dev, PCI_DEVICE_ID); + + if ((cpu_id != CPUID_TIGERLAKE_A0) && (cpu_id != CPUID_TIGERLAKE_B0)) + return false; + + return ((mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2) || + (mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2)); +} + +static int get_disable_mask(struct soc_intel_tigerlake_config *config) +{ + int disable_mask; + + /* Disable any sub-states requested by mainboard */ + disable_mask = config->LpmStateDisableMask; + + /* UP3 does not support S0i2.2/S0i3.3/S0i3.4 */ + if (platform_is_up3()) + disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2; + + /* If external bypass is not used, S0i3 isn't recommended. */ + if (config->external_bypass == false) + disable_mask |= LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4; + + /* If external clock gating is not implemented, S0i3.4 isn't recommended. */ + if (config->external_clk_gated == false) + disable_mask |= LPM_S0i3_4; + + /* + * If external phy gating is not implemented, + * S0i3.3/S0i3.4/S0i2.2 are not recommended. + */ + if (config->external_phy_gated == false) + disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2; + + /* If CNVi or ISH is used, S0i3.2/S0i3.3/S0i3.4 cannot be achieved. */ + if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_BT)) || + is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) || + is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_ISH))) + disable_mask |= LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4; + + return disable_mask; +} + static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_tigerlake_config *config; @@ -234,7 +286,7 @@ * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4 */ - params->LpmStateEnableMask = LPM_S0iX_ALL & ~config->LpmStateDisableMask; + params->LpmStateEnableMask = LPM_S0iX_ALL & ~get_disable_mask(config); /* * Power Optimizer for DMI and SATA. -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 40 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: devicetree: Fix typo in *Coprocessor* in comment
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50385 ) Change subject: mb/google/zork: devicetree: Fix typo in *Coprocessor* in comment ...................................................................... mb/google/zork: devicetree: Fix typo in *Coprocessor* in comment Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants) Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 9b0dd9a..8bc87f7 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -264,7 +264,7 @@ device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocesor + device pci 0.2 on end # Crypto Coprocessor device pci 0.3 on # USB 3.1 chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index a3c4573..f354991 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -266,7 +266,7 @@ device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocesor + device pci 0.2 on end # Crypto Coprocessor device pci 0.3 on # USB 3.1 chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/50385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54 Gerrit-Change-Number: 50385 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi: Fix Coverity Scan report
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50352 ) Change subject: acpi: Fix Coverity Scan report ...................................................................... acpi: Fix Coverity Scan report Fix the issue that return value "r" in line 534 will get overwritten problem. BUG=CID 1445995 TEST=Build sucessful and boot up in QEMU Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Icf760b142cfecfed7c929c15ad190ac74df027b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50352 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/arch/x86/acpi_bert_storage.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Francois Toguo Fotso: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index f1dcf47..b07b67e 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -534,7 +534,7 @@ r = bert_append_genproc(status); else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) r = bert_append_ia32x64(status); - if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) + else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) r = bert_append_fw_err(status); /* else if other types not implemented */ else -- To view, visit https://review.coreboot.org/c/coreboot/+/50352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf760b142cfecfed7c929c15ad190ac74df027b1 Gerrit-Change-Number: 50352 Gerrit-PatchSet: 2 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Remove unused <boot_device.h>
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50201 ) Change subject: src: Remove unused <boot_device.h> ...................................................................... src: Remove unused <boot_device.h> Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/spi/flashconsole.c M src/drivers/spi/spi_flash.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/samsung/exynos5250/spi.c 4 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index d5c4382..679c814 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -2,7 +2,6 @@ #include <commonlib/helpers.h> #include <commonlib/region.h> -#include <boot_device.h> #include <fmap.h> #include <console/console.h> #include <console/flash.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 2406a90..b674749 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <boot_device.h> #include <boot/coreboot_tables.h> +#include <commonlib/region.h> #include <console/console.h> #include <string.h> #include <spi-generic.h> diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 62c274b..c7dec5c 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <boot_device.h> #include <cbfs.h> #include <commonlib/cbfs.h> #include <commonlib/region.h> diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index 879d04a..e630090 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -2,7 +2,7 @@ #include <device/mmio.h> #include <assert.h> -#include <boot_device.h> +#include <commonlib/region.h> #include <console/console.h> #include <soc/clk.h> #include <soc/gpio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615 Gerrit-Change-Number: 50201 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/prodrive/hermes: Set Port C VREF as per EEPROM config
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50396 ) Change subject: mb/prodrive/hermes: Set Port C VREF as per EEPROM config ...................................................................... mb/prodrive/hermes: Set Port C VREF as per EEPROM config Configure Port C VREF according to the settings in the EEPROM. Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/prodrive/hermes/hda_verb.c 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index 473a286..be7dbb4 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -172,6 +172,23 @@ AZALIA_ARRAY_SIZES; +static u32 get_port_c_vref_cfg(uint8_t blue_rear_vref) +{ + switch (blue_rear_vref) { + default: + case 0: + return 0x02040000; + case 1: + return 0x02041000; + case 2: + return 0x02044000; + case 3: + return 0x02045000; + case 4: + return 0x02046000; + } +} + static u32 get_internal_audio_cfg(uint8_t internal_audio_connection) { switch (internal_audio_connection) { @@ -208,6 +225,8 @@ const u32 verbs[] = { AZALIA_PIN_CFG(0, 0x1b, config), + 0x0205000d, + get_port_c_vref_cfg(board_cfg->blue_rear_vref), }; azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); -- To view, visit https://review.coreboot.org/c/coreboot/+/50396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Gerrit-Change-Number: 50396 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/prodrive/hermes: Configure 'internal audio'
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50389 ) Change subject: mb/prodrive/hermes: Configure 'internal audio' ...................................................................... mb/prodrive/hermes: Configure 'internal audio' Implement `mainboard_azalia_program_runtime_verbs` to configure the Realtek ALC888 codec according to the settings in the EEPROM. The encoding of the `internal_audio_connection` field is: 0: Disabled 1: Front HP out 2: Internal speaker Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/prodrive/hermes/hda_verb.c 1 file changed, 44 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index 59b8aa6..473a286 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/azalia_device.h> +#include <types.h> + +#include "variants/baseboard/include/eeprom.h" const u32 cim_verb_data[] = { 0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */ @@ -168,3 +171,44 @@ const u32 pc_beep_verbs[0] = {}; AZALIA_ARRAY_SIZES; + +static u32 get_internal_audio_cfg(uint8_t internal_audio_connection) +{ + switch (internal_audio_connection) { + default: + case 0: + return AZALIA_PIN_CFG_NC(0); + case 1: + return 0x022a4c40; + case 2: + return AZALIA_PIN_DESC( + INTEGRATED, + INTERNAL, + NA, + SPEAKER, + TYPE_UNKNOWN, + COLOR_UNKNOWN, + false, + 0xf, + 0); + } +} + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if (viddid != 0x10ec0888) + return; + + const struct eeprom_board_settings *const board_cfg = get_board_settings(); + + if (!board_cfg) + return; + + const u32 config = get_internal_audio_cfg(board_cfg->internal_audio_connection); + + const u32 verbs[] = { + AZALIA_PIN_CFG(0, 0x1b, config), + }; + + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f Gerrit-Change-Number: 50389 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/azalia_device: Add mainboard hook to program codecs
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50388 ) Change subject: device/azalia_device: Add mainboard hook to program codecs ...................................................................... device/azalia_device: Add mainboard hook to program codecs On some mainboards, codec configuration depends on settings that are only known at runtime, which is impossible to specify using one verb table. Add an optional `mainboard_azalia_program_runtime_verbs` hook where mainboards can program runtime-dependent codec verbs. Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50388 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/azalia_device.c M src/include/device/azalia_device.h 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 5a3a5de..1a57be1 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -210,6 +210,10 @@ return 0; } +__weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ +} + static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; @@ -246,6 +250,8 @@ /* 3 */ azalia_program_verb_table(base, verb, verb_size); printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); + + mainboard_azalia_program_runtime_verbs(base, reg32); } static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index ce8c0d1..9010507 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -26,6 +26,9 @@ void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; +/* Optional hook to program codec settings that are only known at runtime */ +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid); + extern const u32 cim_verb_data[]; extern const u32 cim_verb_data_size; extern const u32 pc_beep_verbs[]; -- To view, visit https://review.coreboot.org/c/coreboot/+/50388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70 Gerrit-Change-Number: 50388 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/azalia_device: Add function to program a verb table
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50387 ) Change subject: device/azalia_device: Add function to program a verb table ...................................................................... device/azalia_device: Add function to program a verb table On some boards, Azalia configuration depends on config settings that are not known at compile-time. Expose a function to program a verb table, to be used in subsequent commits. Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50387 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/azalia_device.c M src/include/device/azalia_device.h 2 files changed, 24 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 8e5998c..5a3a5de 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -188,12 +188,33 @@ return -1; } +static int azalia_write_verb(u8 *base, u32 verb) +{ + if (wait_for_ready(base) < 0) + return -1; + + write32(base + HDA_IC_REG, verb); + + return wait_for_valid(base); +} + +int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size) +{ + if (!verbs) + return 0; + + for (u32 i = 0; i < verb_size; i++) { + if (azalia_write_verb(base, verbs[i]) < 0) + return -1; + } + return 0; +} + static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; u32 verb_size; - int i; printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); @@ -223,15 +244,7 @@ printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size); /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } + azalia_program_verb_table(base, verb, verb_size); printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); } diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 1b4e769..ce8c0d1 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -22,6 +22,7 @@ int azalia_enter_reset(u8 *base); int azalia_exit_reset(u8 *base); u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb); +int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; -- To view, visit https://review.coreboot.org/c/coreboot/+/50387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512 Gerrit-Change-Number: 50387 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/azalia_device.c: Correct print format
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50386 ) Change subject: device/azalia_device.c: Correct print format ...................................................................... device/azalia_device.c: Correct print format The type of `verb_size` is unsigned, thus use `%u` to print its value. Change-Id: I2b353b940e881dc8b5f0b902509d97d89c997a70 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50386 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/azalia_device.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index e383821..8e5998c 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -220,7 +220,7 @@ printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); return; } - printk(BIOS_DEBUG, "azalia_audio: verb_size: %d\n", verb_size); + printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size); /* 3 */ for (i = 0; i < verb_size; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/50386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b353b940e881dc8b5f0b902509d97d89c997a70 Gerrit-Change-Number: 50386 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Correct DDR3 turnaround table
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49388 ) Change subject: nb/intel/x4x: Correct DDR3 turnaround table ...................................................................... nb/intel/x4x: Correct DDR3 turnaround table Comparing against MRC, looks like the values for TA3 and TA4 are backwards. All of them. Thus, correct the tables accordingly. Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works. Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4 Tested-by: Michael Büchler <michael.buechler(a)posteo.net> Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michael Büchler <michael.buechler(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Michael Büchler: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 16e257f..2389b5f 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -428,22 +428,22 @@ static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ - {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ + {0x9, 0x7, 0x9, 0x7}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ }, { /* DDR3 1066 */ {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ - {0x9, 0x7, 0x7, 0x9}, /* CL = 6 */ + {0x9, 0x7, 0x9, 0x7}, /* CL = 6 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 7 */ - {0x9, 0x7, 0x9, 0x7} /* CL = 8 */ + {0x9, 0x7, 0x7, 0x9} /* CL = 8 */ }, { /* DDR3 1333 */ {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ {0x0, 0x0, 0x0, 0x0}, /* CL = 6 - Not supported */ {0x0, 0x0, 0x0, 0x0}, /* CL = 7 - Not supported */ - {0x9, 0x7, 0x9, 0x8}, /* CL = 8 */ - {0x9, 0x7, 0xA, 0x7}, /* CL = 9 */ - {0x9, 0x7, 0xB, 0x6}, /* CL = 10 */ + {0x9, 0x7, 0x8, 0x9}, /* CL = 8 */ + {0x9, 0x7, 0x7, 0xa}, /* CL = 9 */ + {0x9, 0x7, 0x6, 0xb}, /* CL = 10 */ } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/49388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4 Gerrit-Change-Number: 49388 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2021