coreboot-gerrit February 2021

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Change in coreboot[master]: coreboot_table: Use precision when printing lb_gpio name
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49496 ) Change subject: coreboot_table: Use precision when printing lb_gpio name ...................................................................... coreboot_table: Use precision when printing lb_gpio name The lb_gpio coreboot table entries use name fields fixed to 16 bytes. GCC will not allow creating a static initializer for such a field with a string of more than 16 characters... but exactly 16 characters is fine, meaning there's no room for the terminating NUL byte. The payloads (at least depthcharge) can deal with this as well because they're checking the size when looking at that table entry, but our printk("%16s") does not and will happily walk over the end until somewhere else in memory we finally find the next NUL byte. We should probably try to avoid strings of exactly 16 characters in this field anyway, just in case -- but since GCC doesn't warn about them they can easily slip back in. So solve this bug by also adding a precision field to the printk, which will make it stop overrunning the string. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ifd7beef00d828f9dc2faa4747eace6ac4ca41899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49496 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/lib/coreboot_table.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 5f8c69b..29be857 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -165,7 +165,7 @@ " NAME | PORT | POLARITY | VALUE\n", gpios->count); for (g = &gpios->gpios[0]; g < &gpios->gpios[gpios->count]; g++) { - printk(BIOS_INFO, "%16s | ", g->name); + printk(BIOS_INFO, "%16.16s | ", g->name); if (g->port == -1) printk(BIOS_INFO, " undefined | "); else -- To view, visit https://review.coreboot.org/c/coreboot/+/49496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd7beef00d828f9dc2faa4747eace6ac4ca41899 Gerrit-Change-Number: 49496 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp/bootblock.c: Remove unused includes
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50222 ) Change subject: mb/intel/adlrvp/bootblock.c: Remove unused includes ...................................................................... mb/intel/adlrvp/bootblock.c: Remove unused includes Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50222 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/intel/adlrvp/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c index 95f7497..211fcf9 100644 --- a/src/mainboard/intel/adlrvp/bootblock.c +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <bootblock_common.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Gerrit-Change-Number: 50222 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Kyösti Mälkki. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50461 ) Change subject: sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38 Gerrit-Change-Number: 50461 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 07:26:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp/bootblock.c: Remove unused includes
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50222 ) Change subject: mb/intel/adlrvp/bootblock.c: Remove unused includes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Gerrit-Change-Number: 50222 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 07:26:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu-q35/bootblock.c: Remove unused includes
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50220 ) Change subject: mb/emulation/qemu-q35/bootblock.c: Remove unused includes ...................................................................... mb/emulation/qemu-q35/bootblock.c: Remove unused includes Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50220 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/emulation/qemu-q35/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index e17c8ee..4a9a52f 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -4,7 +4,6 @@ #include <bootblock_common.h> #include <southbridge/intel/common/early_spi.h> #include <southbridge/intel/i82801ix/i82801ix.h> -#include <console/console.h> #include "q35.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/50220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645 Gerrit-Change-Number: 50220 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu-q35/bootblock.c: Remove unused includes
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50220 ) Change subject: mb/emulation/qemu-q35/bootblock.c: Remove unused includes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645 Gerrit-Change-Number: 50220 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 07:26:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50221 ) Change subject: mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes ...................................................................... mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50221 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/gizmosphere/gizmo2/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/mainboard/gizmosphere/gizmo2/bootblock.c b/src/mainboard/gizmosphere/gizmo2/bootblock.c index 3fe9351..ccd8ec1 100644 --- a/src/mainboard/gizmosphere/gizmo2/bootblock.c +++ b/src/mainboard/gizmosphere/gizmo2/bootblock.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/acpimmio.h> #include <bootblock_common.h> void bootblock_mainboard_early_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/50221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971 Gerrit-Change-Number: 50221 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/voxel: Add settings for noise mitgation
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50293 ) Change subject: mb/google/volteer/var/voxel: Add settings for noise mitgation ...................................................................... mb/google/volteer/var/voxel: Add settings for noise mitgation Enable acoustic noise mitgation for volteer platforms. BUG=b:179328166 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Sheng-Liang Pan: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 879086f..ed90069 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -19,6 +19,17 @@ # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + device domain 0 on device ref dptf on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/50293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171 Gerrit-Change-Number: 50293 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45002 ) Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size ...................................................................... soc/intel/{cnl,skl}: Add alignment check for TSEG base and size Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG base and size) to remaining SoCs. Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/skylake/smmrelocate.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 05bd1f7..7d189ea 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -152,6 +152,12 @@ const u32 rmask = ~(4 * KiB - 1); smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n"); + return; + } + smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 05bd1f7..7d189ea 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -152,6 +152,12 @@ const u32 rmask = ~(4 * KiB - 1); smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n"); + return; + } + smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Gerrit-Change-Number: 45002 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Enable external bypass, clkgate & phygate
by Patrick Georgi (Code Review) 10 Feb '21

10 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50290 ) Change subject: mb/google/volteer: Enable external bypass, clkgate & phygate ...................................................................... mb/google/volteer: Enable external bypass, clkgate & phygate This change sets the soc config options for external_bypass, external_clk_gate and external_phy_gate. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Sukumar Ghorai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ccde132..6a826c0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -255,6 +255,15 @@ # Enable DPTF register "dptf_enable" = "1" + # Enable External Bypass + register "external_bypass" = "1" + + # Enable External Clk Gate + register "external_clk_gated" = "1" + + # Enable External Phy Gate + register "external_phy_gated" = "1" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 38, -- To view, visit https://review.coreboot.org/c/coreboot/+/50290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Gerrit-Change-Number: 50290 Gerrit-PatchSet: 7 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021