coreboot-gerrit December 2021

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Change in coreboot[master]: devicetree: Check destination size while flattening
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41201 ) Change subject: devicetree: Check destination size while flattening ...................................................................... devicetree: Check destination size while flattening * Check that destination buffer doesn't overflow while flattening * Add 128 bytes to the requested space for the FDT in fit_payload.c Change-Id: Ia8300df1abd012d286c10d12cc99bdc05c2710d8 Signed-off-… [View More]by: Patrick Rudolph <siro(a)das-labor.org> --- M src/include/device_tree.h M src/lib/device_tree.c M src/lib/fit_payload.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c 4 files changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/41201/1 diff --git a/src/include/device_tree.h b/src/include/device_tree.h index bd0d151..ddfb6e5 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -116,8 +116,8 @@ /* Figure out how big a device tree would be if it were flattened. */ uint32_t dt_flat_size(const struct device_tree *tree); -/* Flatten a device tree into the buffer pointed to by dest. */ -void dt_flatten(const struct device_tree *tree, void *dest); +/* Flatten a device tree into the buffer with size len pointed to by dest. */ +void dt_flatten(const struct device_tree *tree, void *dest, size_t len); void dt_print_node(const struct device_tree_node *node); /* Read #address-cells and #size-cells properties from a node. */ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index cb81d32..5d4b2b0 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -421,14 +421,21 @@ *strings_start = dstrings; } -void dt_flatten(const struct device_tree *tree, void *start_dest) +void dt_flatten(const struct device_tree *tree, void *start_dest, size_t len) { uint8_t *dest = (uint8_t *)start_dest; + uint8_t *dest_max = ((uint8_t *)start_dest) + len; + + if ((dest + tree->header_size) > dest_max) + goto err; memcpy(dest, tree->header, tree->header_size); struct fdt_header *header = (struct fdt_header *)dest; dest += tree->header_size; + if ((dest + sizeof(uint64_t) * 2) > dest_max) + goto err; + struct device_tree_reserve_map_entry *entry; list_for_each(entry, tree->reserve_map, list_node) dt_flatten_map_entry(entry, (void **)&dest); @@ -439,6 +446,9 @@ uint32_t strings_size = 0; dt_flat_node_size(tree->root, &struct_size, &strings_size); + if ((dest + struct_size) > dest_max) + goto err; + uint8_t *struct_start = dest; header->structure_offset = htobe32(dest - (uint8_t *)start_dest); header->structure_size = htobe32(struct_size); @@ -447,6 +457,9 @@ *((uint32_t *)dest) = htobe32(FDT_TOKEN_END); dest += sizeof(uint32_t); + if ((dest + strings_size) > dest_max) + goto err; + uint8_t *strings_start = dest; header->strings_offset = htobe32(dest - (uint8_t *)start_dest); header->strings_size = htobe32(strings_size); @@ -456,6 +469,11 @@ (void **)&strings_start); header->totalsize = htobe32(dest - (uint8_t *)start_dest); + + return; +err: + printk(BIOS_CRIT, "%s: Buffer overflowed (used %d, max %zd) while flattening devicetree\n", + __func__, (dest - (uint8_t *)start_dest), len); } diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 9cf1542..1b97ad9 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -23,7 +23,7 @@ printk(BIOS_INFO, "FIT: Flattening FDT to %p\n", (void *)fdt->offset); - dt_flatten(dt, (void *)fdt->offset); + dt_flatten(dt, (void *)fdt->offset, fdt->size); prog_segment_loaded(fdt->offset, fdt->size, 0); } @@ -219,7 +219,8 @@ /* Collect infos for fit_payload_arch */ kernel.size = config->kernel->size; - fdt.size = dt_flat_size(dt); + /* Add additional space for fit_add_ramdisk() */ + fdt.size = dt_flat_size(dt) + 128; initrd.size = config->ramdisk ? config->ramdisk->size : 0; /* Invoke arch specific payload placement and fixups */ diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index c270857..3cffb97 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -96,7 +96,7 @@ return; } - dt_flatten(tree, dt); + dt_flatten(tree, dt, dt_flat_size(tree)); /* update HLS */ for (int i = 0; i < CONFIG_MAX_CPUS; i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/41201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8300df1abd012d286c10d12cc99bdc05c2710d8 Gerrit-Change-Number: 41201 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: emulation/qemu-i440fx: Add \_SB.PCI0.MBRS
by Paul Menzel (Code Review) 09 Jun '23

09 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38304 ) Change subject: emulation/qemu-i440fx: Add \_SB.PCI0.MBRS ...................................................................... emulation/qemu-i440fx: Add \_SB.PCI0.MBRS Linux 5.4.8 shows the ACPI error below. [ 0.732324] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.MBRS], AE_NOT_FOUND (20190816/dswload2-159) [ 0.732784] ACPI Error: AE_NOT_FOUND, During name … [View More]

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Change in coreboot[master]: Documentation/mainboard/lenovo/t420s.md: Add documentation for Lenovo...
by David Gebski (Code Review) 09 Jun '23

09 Jun '23

David Gebski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41484 ) Change subject: Documentation/mainboard/lenovo/t420s.md: Add documentation for Lenovo T420s ...................................................................... Documentation/mainboard/lenovo/t420s.md: Add documentation for Lenovo T420s Borrowed text mostly from documentation for Lenovo T420. Added two images showing the pinout. Signed-off-by: Zalckos <mail(a)davidgebski.nl> Change-… [View More]Id: I9fae5cfd596da144f2161ad35323cb2a6de645a9 --- A Documentation/mainboard/lenovo/t420s.md A Documentation/mainboard/lenovo/t420s_board.jpg A Documentation/mainboard/lenovo/t420s_rpi.jpg 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/41484/1 diff --git a/Documentation/mainboard/lenovo/t420s.md b/Documentation/mainboard/lenovo/t420s.md new file mode 100644 index 0000000..ce848c5 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s.md @@ -0,0 +1,22 @@ +# Lenovo T420s + +## Flashing instructions +The flash IC is located at the bottom center of the mainboard. Sadly, +access to the IC is blocked by the magnesum frame, so you need to disassemble +the entire laptop and remove the mainboard. + +Below is a picture of IC on the mainboard with clip attached, and a picture of the Raspberry Pi with cables attached. In this case it's a Winbond flash chip "W25Q64.V". + +![t420s_board](t420s_board.jpg) +![t420s_rpi](t420s_rpi.jpg) + + +For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and +the general [flashing tutorial]. + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md + diff --git a/Documentation/mainboard/lenovo/t420s_board.jpg b/Documentation/mainboard/lenovo/t420s_board.jpg new file mode 100644 index 0000000..b99ce6e --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s_board.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/t420s_rpi.jpg b/Documentation/mainboard/lenovo/t420s_rpi.jpg new file mode 100644 index 0000000..e7b7626 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s_rpi.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/41484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fae5cfd596da144f2161ad35323cb2a6de645a9 Gerrit-Change-Number: 41484 Gerrit-PatchSet: 1 Gerrit-Owner: David Gebski Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: superio/winbond/w83627dhg: Boards use common config entry/exit function
by Keith Hui (Code Review) 09 Jun '23

09 Jun '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40964 ) Change subject: superio/winbond/w83627dhg: Boards use common config entry/exit function ...................................................................... superio/winbond/w83627dhg: Boards use common config entry/exit function These 4 boards, using this super I/O, do more early init on it than just enabling early serial. Change them to use the common config entry/exit function. Allows to … [View More]drop the duplicate just this chip holds. Change-Id: Ia3cbf6fa9a7719fc420559b9343786c1f66858a4 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p5gc-mx/early_init.c M src/mainboard/asus/p5ql-em/early_init.c M src/mainboard/asus/p5qpl-am/early_init.c M src/mainboard/intel/dg41wv/early_init.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/40964/1 diff --git a/src/mainboard/asus/p5gc-mx/early_init.c b/src/mainboard/asus/p5gc-mx/early_init.c index 4a17c37..be43fba 100644 --- a/src/mainboard/asus/p5gc-mx/early_init.c +++ b/src/mainboard/asus/p5gc-mx/early_init.c @@ -27,7 +27,7 @@ int need_reset = 0; u8 reg, old_reg; - pnp_enter_ext_func_mode(GPIO_DEV); + pnp_enter_conf_state(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); reg = 0x9a; @@ -54,7 +54,7 @@ pnp_write_config(GPIO_DEV, 0xe1, reg); need_reset += ((reg & 0x20) != (old_reg & 0x20)); - pnp_exit_ext_func_mode(GPIO_DEV); + pnp_exit_conf_state(GPIO_DEV); return need_reset; } diff --git a/src/mainboard/asus/p5ql-em/early_init.c b/src/mainboard/asus/p5ql-em/early_init.c index 3803801..1301018 100644 --- a/src/mainboard/asus/p5ql-em/early_init.c +++ b/src/mainboard/asus/p5ql-em/early_init.c @@ -67,7 +67,7 @@ break; } - pnp_enter_ext_func_mode(GPIO_DEV); + pnp_enter_conf_state(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); /* @@ -99,7 +99,7 @@ old_reg = pnp_read_config(GPIO_DEV, 0xf5); /* GPIO4x data */ pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); need_reset += ((reg & 0x1) != (old_reg & 0x1)); - pnp_exit_ext_func_mode(GPIO_DEV); + pnp_exit_conf_state(GPIO_DEV); return need_reset; } diff --git a/src/mainboard/asus/p5qpl-am/early_init.c b/src/mainboard/asus/p5qpl-am/early_init.c index afcd531..18cb314 100644 --- a/src/mainboard/asus/p5qpl-am/early_init.c +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -69,7 +69,7 @@ break; } - pnp_enter_ext_func_mode(GPIO_DEV); + pnp_enter_conf_state(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); if (CONFIG(BOARD_ASUS_P5QPL_AM)) { @@ -121,7 +121,7 @@ pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); need_reset += ((reg & 0x18) != (old_reg & 0x18)); } - pnp_exit_ext_func_mode(GPIO_DEV); + pnp_exit_conf_state(GPIO_DEV); return need_reset; } diff --git a/src/mainboard/intel/dg41wv/early_init.c b/src/mainboard/intel/dg41wv/early_init.c index 584b936..c8d7c67 100644 --- a/src/mainboard/intel/dg41wv/early_init.c +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -25,12 +25,12 @@ void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); pnp_set_logical_device(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x2c, 0x13); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -- To view, visit https://review.coreboot.org/c/coreboot/+/40964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3cbf6fa9a7719fc420559b9343786c1f66858a4 Gerrit-Change-Number: 40964 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: superio/nuvoton/*: Standardise config state entry/exit functions
by Keith Hui (Code Review) 09 Jun '23

09 Jun '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40963 ) Change subject: superio/nuvoton/*: Standardise config state entry/exit functions ...................................................................... superio/nuvoton/*: Standardise config state entry/exit functions Rename nuvoton_pnp_{enter,exit}_conf_state() to pnp_{enter,exit}_conf_state() to match other Super I/Os. Part of an attempt to standardise the pre-RAM API across all Super I/Os. … [View More]Change-Id: I238808b36545f3595a1b1a007ffe5dd41b448231 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asrock/b75pro3-m/early_init.c M src/mainboard/asrock/b85m_pro4/bootblock.c M src/mainboard/asrock/g41c-gs/early_init.c M src/mainboard/asrock/h81m-hds/bootblock.c M src/mainboard/asus/h61m-cs/early_init.c M src/mainboard/asus/p8h61-m_pro/early_init.c M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/asus/p8z77-v_lx2/early_init.c M src/mainboard/supermicro/x10slm-f/bootblock.c M src/superio/nuvoton/common/early_serial.c M src/superio/nuvoton/common/nuvoton.h 11 files changed, 22 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40963/1 diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 552e664..7a4a30c 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -30,14 +30,14 @@ void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ - nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); pnp_set_logical_device(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x1c, 0x80); pnp_write_config(SERIAL_DEV, 0x27, 0x80); pnp_write_config(SERIAL_DEV, 0x2a, 0x60); - nuvoton_pnp_exit_conf_state(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index 5f91b29..2e72b22 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -12,7 +12,7 @@ void mainboard_config_superio(void) { - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + pnp_enter_conf_state(GLOBAL_DEV); /* Select HWM/LED functions instead of floppy functions */ pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); @@ -22,7 +22,7 @@ pnp_set_logical_device(ACPI_DEV); pnp_write_config(ACPI_DEV, 0xe4, 0x70); - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + pnp_exit_conf_state(GLOBAL_DEV); /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asrock/g41c-gs/early_init.c b/src/mainboard/asrock/g41c-gs/early_init.c index d35bb5d..209885a 100644 --- a/src/mainboard/asrock/g41c-gs/early_init.c +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -29,14 +29,14 @@ { /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { - nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); + pnp_enter_conf_state(SERIAL_DEV_R2); pnp_set_logical_device(SERIAL_DEV_R2); pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); - nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); + pnp_exit_conf_state(SERIAL_DEV_R2); nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); } else { winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asrock/h81m-hds/bootblock.c b/src/mainboard/asrock/h81m-hds/bootblock.c index f3fb2c2..f5bbf6f 100644 --- a/src/mainboard/asrock/h81m-hds/bootblock.c +++ b/src/mainboard/asrock/h81m-hds/bootblock.c @@ -15,7 +15,7 @@ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); /* Select HWM/LED functions instead of floppy functions. */ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); @@ -32,5 +32,5 @@ pnp_set_logical_device(IR_DEV); pnp_write_config(IR_DEV, 0xf1, 0x5c); - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); + pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); } diff --git a/src/mainboard/asus/h61m-cs/early_init.c b/src/mainboard/asus/h61m-cs/early_init.c index 1b9adb4..45459a4 100644 --- a/src/mainboard/asus/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61m-cs/early_init.c @@ -32,10 +32,10 @@ void bootblock_mainboard_early_init(void) { - nuvoton_pnp_enter_conf_state(SIO_DEV); + pnp_enter_conf_state(SIO_DEV); pnp_set_logical_device(ACPI_DEV); pnp_write_config(ACPI_DEV, 0xe4, 0x10); - nuvoton_pnp_exit_conf_state(SIO_DEV); + pnp_exit_conf_state(SIO_DEV); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) diff --git a/src/mainboard/asus/p8h61-m_pro/early_init.c b/src/mainboard/asus/p8h61-m_pro/early_init.c index 582366d..f6eb812 100644 --- a/src/mainboard/asus/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/p8h61-m_pro/early_init.c @@ -33,7 +33,7 @@ void bootblock_mainboard_early_init(void) { /* Enable UART */ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + pnp_enter_conf_state(GLOBAL_DEV); /* Select SIO pin states. */ pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); @@ -47,7 +47,7 @@ pnp_set_logical_device(SERIAL_DEV); - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + pnp_exit_conf_state(GLOBAL_DEV); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 687cbfd..eb0df1c 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -38,12 +38,12 @@ void bootblock_mainboard_early_init(void) { /* Setup COM/UART */ - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + pnp_enter_conf_state(GLOBAL_DEV); /* TODO / FIXME: Setup Multifuncion/SIO pins for COM */ pnp_set_logical_device(SERIAL_DEV); - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + pnp_exit_conf_state(GLOBAL_DEV); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c index cbbf9dc..5a7b4cb 100644 --- a/src/mainboard/asus/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8z77-v_lx2/early_init.c @@ -32,7 +32,7 @@ void bootblock_mainboard_early_init(void) { - nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + pnp_enter_conf_state(GLOBAL_DEV); /* Select SIO pin states */ pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); @@ -47,7 +47,7 @@ pnp_set_logical_device(ACPI_DEV); pnp_write_config(ACPI_DEV, 0xe4, 0x10); - nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + pnp_exit_conf_state(GLOBAL_DEV); /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm-f/bootblock.c index c0d4502..64b5e6d 100644 --- a/src/mainboard/supermicro/x10slm-f/bootblock.c +++ b/src/mainboard/supermicro/x10slm-f/bootblock.c @@ -26,7 +26,7 @@ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); /* Select HWM/LED functions instead of floppy functions. */ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); @@ -36,5 +36,5 @@ pnp_set_logical_device(ACPI_DEV); pnp_write_config(ACPI_DEV, 0xe4, 0x70); - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); + pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); } diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index ed31b72..b709969 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -31,7 +31,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -39,7 +39,7 @@ } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); @@ -48,7 +48,7 @@ /* Bring up early serial debugging output before the RAM is initialized. */ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { - nuvoton_pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A)) /* Route COM A to GPIO8 pin group */ @@ -66,5 +66,5 @@ pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); - nuvoton_pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index f5b3176..d69548e 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -7,8 +7,6 @@ #include <device/pnp_type.h> #include <stdint.h> -void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev); -void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev); void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NUVOTON_COMMON_PRE_RAM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I238808b36545f3595a1b1a007ffe5dd41b448231 Gerrit-Change-Number: 40963 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: Doc/mb/lenovo/t420s.md: Add documentation for Lenovo T420s
by David Gebski (Code Review) 09 Jun '23

09 Jun '23

David Gebski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41490 ) Change subject: Doc/mb/lenovo/t420s.md: Add documentation for Lenovo T420s ...................................................................... Doc/mb/lenovo/t420s.md: Add documentation for Lenovo T420s Borrowed text mostly from documentation for Lenovo T420. Added two images showing the pinout. Signed-off-by: Zalckos <mail(a)davidgebski.nl> Change-Id: … [View More]Ia2c6701bc8269e73e4af5a9414b7ded77a4d3571 --- A Documentation/mainboard/lenovo/t420s.md A Documentation/mainboard/lenovo/t420s_board.jpg A Documentation/mainboard/lenovo/t420s_rpi.jpg 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41490/1 diff --git a/Documentation/mainboard/lenovo/t420s.md b/Documentation/mainboard/lenovo/t420s.md new file mode 100644 index 0000000..82be80c --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s.md @@ -0,0 +1,22 @@ +# Lenovo T420s + +## Flashing instructions +The flash IC is located at the bottom center of the mainboard. Sadly, access +to the IC is blocked by the magnesium frame, so you need to disassemble the +entire laptop and remove the mainboard. + +Below is a picture of IC on the mainboard with clip attached, and a picture of +the Raspberry Pi with cables attached. In this case it's a Winbond flash chip +"W25Q64.V". + +![t420s_board](t420s_board.jpg) +![t420s_rpi](t420s_rpi.jpg) + +For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and +the general [flashing tutorial]. + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t420s_board.jpg b/Documentation/mainboard/lenovo/t420s_board.jpg new file mode 100644 index 0000000..3ec4201 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s_board.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/t420s_rpi.jpg b/Documentation/mainboard/lenovo/t420s_rpi.jpg new file mode 100644 index 0000000..6fe204c --- /dev/null +++ b/Documentation/mainboard/lenovo/t420s_rpi.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/41490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2c6701bc8269e73e4af5a9414b7ded77a4d3571 Gerrit-Change-Number: 41490 Gerrit-PatchSet: 1 Gerrit-Owner: David Gebski Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: [UNTESTED] intel/stm: Introduce stm_update_smm_info()
by Nico Huber (Code Review) 09 Jun '23

09 Jun '23

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Change in coreboot[master]: [UNTESTED] cpu/x86/smm: Drop now unused `num_cpus` param
by Nico Huber (Code Review) 09 Jun '23

09 Jun '23

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Change in coreboot[master]: [UNTESTED] intel/stm: Move SMRAM allocations into stm_update_smm_info()
by Nico Huber (Code Review) 09 Jun '23

09 Jun '23

Hello Kyösti Mälkki, Aaron Durbin, Arthur Heymans, cedarhouse1(a)comcast.net, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38769 to review the following change. Change subject: [UNTESTED] intel/stm: Move SMRAM allocations into stm_update_smm_info() ...................................................................... [UNTESTED] intel/stm: Move SMRAM allocations into stm_update_smm_info() Also keep related calculations local to STM code. … [View More]Change-Id: I3aa5915ddeffdabe792b9c30cd72cc39a8f54ca6 --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/security/intel/stm/SmmStm.h M src/security/intel/stm/StmPlatformSmm.c 4 files changed, 39 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38769/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5b34d4b..45f7337 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -746,22 +746,8 @@ /* Setup code checks this callback for validity. */ mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); - if (CONFIG(STM)) { - if (is_smm_enabled()) { - uintptr_t mseg; - - mseg = mp_state.perm_smbase + - (mp_state.perm_smsize - CONFIG_MSEG_SIZE); - - stm_setup(mseg, p->cpu, - perm_smbase, - mp_state.perm_smbase, - runtime->start32_offset); - } else { - printk(BIOS_DEBUG, - "STM not loaded because SMM is not enabled!\n"); - } - } + stm_setup(cpu, mp_state.perm_smbase, mp_state.perm_smsize, + perm_smbase, runtime->start32_offset); } static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index d4a384a..6482c35 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -17,7 +17,6 @@ #include <cpu/x86/cache.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 @@ -314,13 +313,10 @@ /* The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size - * | BIOS resource | - * | list (STM) | - * +-----------------+ <- smram + size - CONFIG_BIOS_RESOURCE_LIST_SIZE * | stacks | - * +-----------------+ <- .. - total_stack_size + * +-----------------+ <- smram + size - total_stack_size * | fxsave area | - * +-----------------+ <- .. - total_stack_size - fxsave_size + * +-----------------+ <- smram + size - total_stack_size - fxsave_size * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE * | handler | @@ -362,10 +358,6 @@ /* Stacks start at the top of the region. */ base = smram; base += size; - - if (CONFIG(STM)) - base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; - params->stack_top = base; /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h index f6ab0bf..58d74c0 100644 --- a/src/security/intel/stm/SmmStm.h +++ b/src/security/intel/stm/SmmStm.h @@ -30,13 +30,14 @@ #if CONFIG(STM) void stm_update_smm_info( uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void stm_setup( + int cpu, uintptr_t perm_smbase, size_t perm_smsize, + uintptr_t staggered_smbase, size_t offset32); #else static inline void stm_update_smm_info(uintptr_t *, size_t *, size_t *) {} +static inline void stm_setup(int, uintptr_t, size_t, uintptr_t, size_t) {} #endif -void stm_setup( - uintptr_t mseg, int cpu, uintptr_t smbase, - uintptr_t smbase_base, uint32_t offset32); /* * Add resources in list to database. Allocate new memory areas as needed. diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index c389afa..c3c3ee8 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -154,10 +154,34 @@ static int stm_load_status = 0; +/* + * We cut off some space from the top of SMRAM and also increase + * the per CPU save-state for the TXT SMM descriptor: + * +--------------------+ <- smram + size + * | MSEG | + * +--------------------+ <- smram + size - MSEG size + * | BIOS Resource List | + * +--------------------+ <- smram + size - MSEG size - BIOS Resource list size + * | SMM module | + * | ... | + * | +-------------+ | + * | + + | + * | + ... + | + * | +-------------+ | + * | + TXT Desc. + | + * | + CPU 1 save + | + * | +-------------+ | + * | + TXT Desc. + | + * | + CPU 0 save + | + * | +-------------+ | + * +--------------------+ <- smram + */ void stm_update_smm_info( uintptr_t *const perm_smbase, size_t *const perm_smsize, size_t *const smm_save_state_size) { + *perm_smsize -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + *smm_save_state_size += sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); /* @@ -169,19 +193,22 @@ *smm_save_state_size = ALIGN_UP(*smm_save_state_size, 0x1000); } -void stm_setup(uintptr_t mseg, int cpu, uintptr_t smbase, - uintptr_t base_smbase, uint32_t offset32) +void stm_setup( + const int cpu, const uintptr_t perm_smbase, const size_t perm_smsize, + const uintptr_t staggered_smbase, const size_t offset32) { msr_t InitMseg; msr_t MsegChk; uintptr_t addr_calc; // used to calculate the stm resource heap area + const uintptr_t mseg = perm_smbase + perm_smsize + CONFIG_BIOS_RESOURCE_LIST_SIZE; + printk(BIOS_DEBUG, "STM: set up for cpu %d\n", cpu); if (cpu == 0) { // need to create the BIOS resource list once // first calculate the location in SMRAM - addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; + addr_calc = perm_smbase + perm_smsize; stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); @@ -204,7 +231,7 @@ cpu, MsegChk.hi, MsegChk.lo); // setup the descriptor for this cpu - setup_smm_descriptor((void *)smbase, (void *) base_smbase, + setup_smm_descriptor((void *)staggered_smbase, (void *)perm_smbase, cpu, offset32); } else { printk(BIOS_DEBUG, -- To view, visit https://review.coreboot.org/c/coreboot/+/38769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa5915ddeffdabe792b9c30cd72cc39a8f54ca6 Gerrit-Change-Number: 38769 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange [View Less]

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Change in coreboot[master]: amdfwtool: Unpack struct `_bios_directory_entry`
by Paul Menzel (Code Review) 09 Jun '23

09 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41154 ) Change subject: amdfwtool: Unpack struct `_bios_directory_entry` ...................................................................... amdfwtool: Unpack struct `_bios_directory_entry` gcc (Debian 10-20200502-1) 10.0.1 20200502 (prerelease) [gcc-10 revision d128356d460:a9ed47dd155:0118d0397f94c307b76aa14abec99347a93da621] shows the warning below. /coreboot/util/amdfwtool/amdfwtool.c: In … [View More]

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