coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/alderlake: Add crashlog trigger on all reset toggle
by Paul Menzel (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Tim Wawrzynczak, Curtis Chen, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59951 ) Change subject: soc/intel/alderlake: Add crashlog trigger on all reset toggle ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59951/comment/564fee59_afc4ab84 PS1, Line 9: This feature should : not be enabled by default. Why? What problem does it cause? -- To view, visit https://review.coreboot.org/c/coreboot/+/59951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Gerrit-Change-Number: 59951 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 10:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Not enable crashlog on all resets by default
by Paul Menzel (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Curtis Chen, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59952 ) Change subject: soc/intel/common: Not enable crashlog on all resets by default ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59952/comment/5d414f9f_482497fa PS1, Line 7: Not Do not … Patchset: PS1: This should be squashed in the parent commit. File src/soc/intel/common/block/crashlog/crashlog.c: https://review.coreboot.org/c/coreboot/+/59952/comment/f8bc011b_a14fceb0 PS1, Line 482: #if CONFIG(SOC_INTEL_CRASHLOG_ON_RESET) Please do that in C code and not the preprocessor. You could also log, that it’s disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/59952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide994c8ddebcbc3645a169cfed76daee496070bb Gerrit-Change-Number: 59952 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 10:27:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/block/systemagent: Do more fine grained resource allocation
by Arthur Heymans (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59845 ) Change subject: soc/block/systemagent: Do more fine grained resource allocation ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/59845/comment/8ada0417_880060be PS1, Line 191: reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); > IIRC, the cacheability of TSEG is ultimately decided by SMRRs, which override MTRR settings. With this patch, I'd expect MTRR usage to increase. Not quite. Often TOLUD is a multiple of 1G, so marking TSEG, which is below TOLUD, as WB instead of UC improves the solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/59845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbceeb31f15ba78c9a241869b5a34cb378096dbb Gerrit-Change-Number: 59845 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 10:26:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Not enable crashlog on all resets by default
by Curtis Chen (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Patrick Rudolph. Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59952 ) Change subject: soc/intel/common: Not enable crashlog on all resets by default ...................................................................... soc/intel/common: Not enable crashlog on all resets by default Using the CONFIG_SOC_INTEL_CRASHLOG_ON_RESET to control the crashlog feature - "Trigger_on_all_resets". BUG=b:202737385 TEST='ls /var/spool/crash/*.bertdump' should be empty after ec apreset. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: Ide994c8ddebcbc3645a169cfed76daee496070bb --- M src/soc/intel/common/block/crashlog/crashlog.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59952/1 diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index c3d0cfd..b9f4417 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -479,8 +479,10 @@ { if (pmc_crashlog_support() && cl_pmc_data_present() && (cl_get_pmc_record_size() > 0)) { +#if CONFIG(SOC_INTEL_CRASHLOG_ON_RESET) cl_pmc_en_gen_on_all_reboot(); printk(BIOS_DEBUG, "Crashlog collection enabled on every reboot.\n"); +#endif cl_get_pmc_sram_data(); } else { printk(BIOS_DEBUG, "Skipping PMC crashLog collection. Data not present.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/59952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide994c8ddebcbc3645a169cfed76daee496070bb Gerrit-Change-Number: 59952 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add crashlog trigger on all reset toggle
by Curtis Chen (Code Review) 07 Dec '21

07 Dec '21

Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59951 ) Change subject: soc/intel/alderlake: Add crashlog trigger on all reset toggle ...................................................................... soc/intel/alderlake: Add crashlog trigger on all reset toggle Trigger on all reset is a feature of the crashlog. This feature should not be enabled by default. Now we add a CONFIG to control it. BUG=b:202737385 TEST='ls /var/spool/crash/*.bertdump' should be empty after ec apreset. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/59951/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 89570b1..92281b2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -339,6 +339,11 @@ help Enables CrashLog. +config SOC_INTEL_CRASHLOG_ON_RESET + def_bool n + help + Enable PMC reset crashlog record. + if STITCH_ME_BIN config CSE_BPDT_VERSION -- To view, visit https://review.coreboot.org/c/coreboot/+/59951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Gerrit-Change-Number: 59951 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/var/gimble4es: Set PsysPmax to 143 W
by Mark Hsieh (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Chia-Ling Hou, Paul Menzel, Ryan Lin, Zhuohao Lee. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59950 ) Change subject: mb/var/gimble4es: Set PsysPmax to 143 W ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I851e0871461a9a9769c6b84f7d8287d989c23f06 Gerrit-Change-Number: 59950 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 10:12:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation
by Mark Hsieh (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59949 ) Change subject: mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb Gerrit-Change-Number: 59949 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Dec 2021 10:10:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/block/systemagent: Do more fine grained resource allocation
by Angel Pons (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59845 ) Change subject: soc/block/systemagent: Do more fine grained resource allocation ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/59845/comment/e48962ad_9fa94f30 PS1, Line 182: printk(BIOS_DEBUG, "%s UC memory: base=0x%lx, size=0x%lx\n", __func__, base_k, size_k); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/59845/comment/0e325e56_a5621483 PS1, Line 191: reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); IIRC, the cacheability of TSEG is ultimately decided by SMRRs, which override MTRR settings. With this patch, I'd expect MTRR usage to increase. -- To view, visit https://review.coreboot.org/c/coreboot/+/59845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbceeb31f15ba78c9a241869b5a34cb378096dbb Gerrit-Change-Number: 59845 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 10:02:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus: add audio codec into SSFC support for ApelE
by Paul2 Huang (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Henry Sun, Paul2 Huang. Hello build bot (Jenkins), Henry Sun, Marco Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59856 to look at the new patch set (#5). Change subject: mb/google/octopus: add audio codec into SSFC support for ApelE ...................................................................... mb/google/octopus: add audio codec into SSFC support for ApelE Add ALC5682I-VS codec support. ALC5682I-VD/ALC5682I-VS load different hid name depending on SSFC. Define SSFC BIT9-11 for codec selection. BUG=b:198722640 BRANCH=octopus TEST=Set CBI SSFC BIT9-11 to select codec, and test audio work Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8 Signed-off-by: Paul Huang <paul2_huang(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/variants/ampton/overridetree.cb M src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/59856/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8 Gerrit-Change-Number: 59856 Gerrit-PatchSet: 5 Gerrit-Owner: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/systemagent: Remove weak functions
by Angel Pons (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Paul Menzel, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59844 ) Change subject: soc/intel/common/systemagent: Remove weak functions ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59844/comment/c365c911_88b705ae PS1, Line 9: an useful > a useful Indeed. This is because `useful` is pronounced as `/ˈjuːsf(ə)l/` which starts with a consonant phoneme. https://review.coreboot.org/c/coreboot/+/59844/comment/b77b0391_c04fa3bf PS1, Line 9: socs nit: SoCs -- To view, visit https://review.coreboot.org/c/coreboot/+/59844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I773311ef6f8d98441ce461343066f8b25c741fbc Gerrit-Change-Number: 59844 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 09:58:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit December 2021