coreboot-gerrit December 2021

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Change in coreboot[master]: util/testing: combine code coverage data
by Paul Fagerburg (Code Review) 07 Dec '21

07 Dec '21

Paul Fagerburg has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59959 ) Change subject: util/testing: combine code coverage data ...................................................................... util/testing: combine code coverage data As part of the `what-jenkins-does` target, combine the code coverage data from all unit tests (currently just coreboot and libpayload). BUG=b:203800199 TEST=`make what-jenkins-does && ls -l coreboot-builds/coverage.info` Change-Id: Id99615ca8279f80a402d5371221b8fd36fb91d55 --- M util/testing/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59959/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id99615ca8279f80a402d5371221b8fd36fb91d55 Gerrit-Change-Number: 59959 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/testing: combine code coverage data
by Paul Fagerburg (Code Review) 07 Dec '21

07 Dec '21

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59959 ) Change subject: util/testing: combine code coverage data ...................................................................... util/testing: combine code coverage data As part of the `what-jenkins-does` target, combine the code coverage data from all unit tests (currently just coreboot and libpayload). BUG=b:203800199 TEST=`make what-jenkins-does && ls -l coreboot-builds/coverage.info` Change-Id: Id99615ca8279f80a402d5371221b8fd36fb91d55 --- M util/testing/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59959/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 1411c7e..f5e8246 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -105,6 +105,8 @@ $(MAKE) unit-tests JUNIT_OUTPUT=y COV=1 (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) unit-tests coverage-report JUNIT_OUTPUT=y COV=1) $(MAKE) coverage-report JUNIT_OUTPUT=y COV=1 + find . -name 'tests.info' -exec cat {} + >$(COREBOOT_BUILD_DIR)/coverage.info + test-basic: test-lint test-tools test-abuild test-payloads test-cleanup -- To view, visit https://review.coreboot.org/c/coreboot/+/59959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id99615ca8279f80a402d5371221b8fd36fb91d55 Gerrit-Change-Number: 59959 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: SeaBIOS: Update stable release to 1.15.0
by Martin Roth (Code Review) 07 Dec '21

07 Dec '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59957 ) Change subject: SeaBIOS: Update stable release to 1.15.0 ...................................................................... SeaBIOS: Update stable release to 1.15.0 SeaBIOS 1.15.0 was released on December 2nd. This updates the stable version from 1.14.0 to 1.15.0 Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ibc526fbddf8a13e7b00e963f9c2e73a9863c9daa --- M payloads/external/SeaBIOS/Kconfig M payloads/external/SeaBIOS/Makefile 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/59957/1 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 9aea2d0..18f2a47 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.14.0" + bool "1.15.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index cdcd426..d908ba8 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=155821a1990b6de78dde5f98fa5ab90e802021e0 +TAG-$(CONFIG_SEABIOS_STABLE)=2dd4b9b3f84019668719344b40dba79d681be41c TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git -- To view, visit https://review.coreboot.org/c/coreboot/+/59957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc526fbddf8a13e7b00e963f9c2e73a9863c9daa Gerrit-Change-Number: 59957 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Combine mem_parts_used.txt
by Karthik Ramasubramanian (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Chris Wang, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59923 ) Change subject: mb/google/guybrush: Combine mem_parts_used.txt ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Gerrit-Change-Number: 59923 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 16:40:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Enable PCIe support for mt8195
by Paul Menzel (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56793 ) Change subject: soc/mediatek: Enable PCIe support for mt8195 ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8195/Makefile.inc: https://review.coreboot.org/c/coreboot/+/56793/comment/96aff797_e219eb3e PS6, Line 72: ramstage-y += ../common/pcie.c pcie.c As discussed on the mailing list [1], this should be user configurable. [1]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/R2X2… -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 15:07:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/amd/pi/00730F01/northbridge.c: remove unneeded global var...
by Felix Held (Code Review) 07 Dec '21

07 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59870 ) Change subject: northbridge/amd/pi/00730F01/northbridge.c: remove unneeded global variables ...................................................................... northbridge/amd/pi/00730F01/northbridge.c: remove unneeded global variables Remove global variables `sblink` and `node_nums` and add function `get_node_nums()` which reads from PCI config once and returns a static variable. TEST=Boot Debian 11 on PC Engines apu3 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59870 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 23 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b56e9ca..42505ab 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -29,8 +29,6 @@ #define PCIE_CAP_AER BIT(5) #define PCIE_CAP_ACS BIT(6) -static unsigned int node_nums; -static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; static struct device *__f1_dev[MAX_NODE_NUMS]; static struct device *__f2_dev[MAX_NODE_NUMS]; @@ -42,6 +40,23 @@ return pcidev_on_root(DEV_CDB + nodeid, fn); } +static struct device *get_mc_dev(void) +{ + return pcidev_on_root(DEV_CDB, 0); +} + +static unsigned int get_node_nums(void) +{ + static unsigned int node_nums; + + if (node_nums) + return node_nums; + + node_nums = ((pci_read_config32(get_mc_dev(), 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + + return node_nums; +} + static void get_fx_devs(void) { int i; @@ -164,6 +179,9 @@ static void create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; + unsigned int sblink; + + sblink = (pci_read_config32(get_mc_dev(), 0x64)>>8) & 7; // don't forget sublink1 /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ @@ -724,7 +742,7 @@ int i; mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t basek, limitk; u32 hole; if (!get_dram_base_limit(i, &basek, &limitk)) @@ -742,7 +760,7 @@ */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t base_k, limit_k; if (!get_dram_base_limit(i, &base_k, &limit_k)) continue; // no memory on this node @@ -788,7 +806,7 @@ #endif idx = 0x10; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t basek, limitk, sizek; // 4 1T if (!get_dram_base_limit(i, &basek, &limitk)) @@ -856,24 +874,6 @@ .acpi_name = domain_acpi_name, }; -static void sysconf_init(struct device *dev) // first node -{ - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] -} - -static void cpu_bus_scan(struct device *dev) -{ - struct device *dev_mc; - - dev_mc = pcidev_on_root(DEV_CDB, 0); - if (!dev_mc) { - printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); - die(""); - } - sysconf_init(dev_mc); -} - static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); @@ -906,7 +906,6 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, - .scan_bus = cpu_bus_scan, }; static void root_complex_enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/59870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20a47f967093ef91355377c164656cabadc30fe6 Gerrit-Change-Number: 59870 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/common/usb: Remove weak function `mtk_usb_prepare()`
by Paul Menzel (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59956 to look at the new patch set (#2). Change subject: soc/mediatek/common/usb: Remove weak function `mtk_usb_prepare()` ...................................................................... soc/mediatek/common/usb: Remove weak function `mtk_usb_prepare()` All SoCs implement it, and a useful implementation is expected, so remove the weak definition. Change-Id: Iaa7806b0430ea5ae1f3c699e6305476b0082e544 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/mediatek/common/usb.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/59956/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa7806b0430ea5ae1f3c699e6305476b0082e544 Gerrit-Change-Number: 59956 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/common/usb: Remove weak function `mtk_usb_prepare()`
by Paul Menzel (Code Review) 07 Dec '21

07 Dec '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59956 ) Change subject: soc/mediatek/common/usb: Remove weak function `mtk_usb_prepare()` ...................................................................... soc/mediatek/common/usb: Remove weak function `mtk_usb_prepare()` All SoCs implement it, so remove it. Change-Id: Iaa7806b0430ea5ae1f3c699e6305476b0082e544 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/mediatek/common/usb.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/59956/1 diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index 52daaac..72bd9e0 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -140,8 +140,6 @@ clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); } -__weak void mtk_usb_prepare(void) { /* do nothing */ } - void setup_usb_host(void) { u3p_msg("Setting up USB HOST controller...\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/59956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa7806b0430ea5ae1f3c699e6305476b0082e544 Gerrit-Change-Number: 59956 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS recovery feature
by build bot (Jenkins) (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 ) Change subject: amdfwtool: Add support for AMD's BIOS recovery feature ...................................................................... Patch Set 44: Verified+1 (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135123): https://review.coreboot.org/c/coreboot/+/57131/comment/a3b6bebf_e53de9cb PS44, Line 1874: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 44 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Tue, 07 Dec 2021 14:38:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in S...
by Felix Held (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Michał Żygowski, Michał Kopeć. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59934 ) Change subject: [TESTME] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > SPIx20 register in BKDG describes only the bit0 (SPI100_ENABLE), the rest is reserved. […] especially bits 8-11 of SPIx20 which are the same bits as bits 0-3 of SPIx21 shouldn't be cleared. I don't think that it make much of a difference for bits 1-7 of SPIx20; those are either reserved or default 0 on Mullins. I just noticed that this function is unused; shouldn't hurt to fix this there too though -- To view, visit https://review.coreboot.org/c/coreboot/+/59934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Gerrit-Change-Number: 59934 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 14:36:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021