coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: soc/intel/cannonlake: Set MAX_CPUS to 16
by Tim Crawford (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Felix Singer, Nico Huber. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52607 ) Change subject: soc/intel/cannonlake: Set MAX_CPUS to 16 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Maximum for Comet Lake is 20, IIRC. system76/bonw14 supports i9-10900K (desktop processor) which has 20 threads. -- To view, visit https://review.coreboot.org/c/coreboot/+/52607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d Gerrit-Change-Number: 52607 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 07 Dec 2021 22:54:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/variant/taniks: Upload memory settings
by Tim Wawrzynczak (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: YH Lin, Joey Peng. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59947 ) Change subject: mb/google/brya/variant/taniks: Upload memory settings ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0794fb94d1f6271de604835ae1d2b20696ee70 Gerrit-Change-Number: 59947 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 22:51:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
by Tim Wawrzynczak (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Cliff Huang, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59855 ) Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ...................................................................... Patch Set 2: (3 comments) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/59855/comment/6fff4c97_2f4acdf7 PS2, Line 39: #define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ > I take this back, LCAP is 0x4c and the last byte is for port number (PN). correct, we just do an 8-bit read at 0x4f instead of the whole 32-bit register 👍 https://review.coreboot.org/c/coreboot/+/59855/comment/db33f581_615abf60 PS2, Line 99: static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp) > Can we merge these two functions by introducing a bool arg for on/off? Sure. https://review.coreboot.org/c/coreboot/+/59855/comment/ed33fc4a_a3cdf6ac PS2, Line 238: static bool mutex_created; > initialize to false, please. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Gerrit-Change-Number: 59855 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 22:50:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
by Tim Wawrzynczak (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Cliff Huang, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59855 to look at the new patch set (#3). Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ...................................................................... soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 For additional power savings during RTD3, the PMC can power-gate the ModPHY lanes that are used by the PCH PCIe root ports. Therefore, using the previous PCIe RP-type detection functions, implement ModPHY PG support for the PCH PCIe RPs. This involves: 1) Adding a mutex so only one power resource accesses the PMC registers at a time 2) OperationRegions to access the PMC's PG registers 3) Adding ModPHY PG enable sequence to _OFF 4) Adding ModPHY PG disable sequence to _ON BUG=b:197983574 TEST=50 S0ix suspend/resume cycles on brya0 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 79 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/59855/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Gerrit-Change-Number: 59855 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Tim Wawrzynczak (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 ) Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... Patch Set 4: (2 comments) File src/mainboard/intel/adlrvp/early_gpio_n.c: https://review.coreboot.org/c/coreboot/+/59937/comment/5db5f6d1_353c207f PS4, Line 14: what about EC_IN_RW smbus? does this platform have DDR or MD? https://review.coreboot.org/c/coreboot/+/59937/comment/7575ecfc_cecb14f4 PS4, Line 16: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), : : /* CPU PCIe vGPIO for RP1 */ : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1), : : /* CPU PCIe vGPIO for RP2 */ : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1), : : /* CPU PCIe vGPIO for RP3 */ : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), Note about these, we have actually found `PLTRST` to be the correct reset type for these PCIe VGPIOs. We have found that if you power down to S5 (but not G3), then power back up to S0, there can be an MCA when the CPU PCIe is used. Setting them to PLTRST ensures the signal gets reset on S5 entry. -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 22:45:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp_n: Add initial code for adl-n variant board
by Tim Wawrzynczak (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Reka Norman, Krishna P Bhat D, Usha P, Kangheui Won. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59915 ) Change subject: mb/intel/adlrvp_n: Add initial code for adl-n variant board ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Gerrit-Change-Number: 59915 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 22:37:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/addw1: Increase max CPUs to 16
by Tim Crawford (Code Review) 07 Dec '21

07 Dec '21

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59964 ) Change subject: mb/system76/addw1: Increase max CPUs to 16 ...................................................................... mb/system76/addw1: Increase max CPUs to 16 The addw1 supports an i9-9980HK and the addw2 uses an i7-10875H. These CPUs have 8 cores and 16 threads. Fixes booting on addw2. Change-Id: I4639b40c3ab9c6d6ad5abbbb3618c750c7d40695 Fixes: 6a93a4524205 ("mb/system76/addw1: Add System76 Adder Workstation 1") Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/addw1/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/59964/1 diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig index c307a7d..64aa12b 100644 --- a/src/mainboard/system76/addw1/Kconfig +++ b/src/mainboard/system76/addw1/Kconfig @@ -61,6 +61,9 @@ config UART_FOR_CONSOLE default 2 +config MAX_CPUS + default 16 + config DIMM_MAX default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4639b40c3ab9c6d6ad5abbbb3618c750c7d40695 Gerrit-Change-Number: 59964 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/intel/adlrvp: Add Kconfig for Alder Lake-N
by Reka Norman (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Krishna P Bhat D, Usha P, Kangheui Won. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59724 ) Change subject: mb/intel/adlrvp: Add Kconfig for Alder Lake-N ...................................................................... Patch Set 5: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/59724/comment/11b98ae1_621d27af PS5, Line 97: default "ADLRVPP" Should this have an entry for "ADLRVPN"? -- To view, visit https://review.coreboot.org/c/coreboot/+/59724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091663590966c174f980e41a31c93c44c7add529 Gerrit-Change-Number: 59724 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 21:54:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE
by Felix Held (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Michał Kopeć, Felix Held. Hello build bot (Jenkins), Michał Żygowski, Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59934 to look at the new patch set (#2). Change subject: sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE ...................................................................... sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities. Haven't checked the reference code, but the register descriptions suggested that the register in Mullins behaves similar to the one in Stoneyridge. Right now this code is unused, but it's probably still a good idea to fix it. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifbd960a9509542b28f03326a3066995540260bef --- M src/southbridge/amd/pi/hudson/early_setup.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59934/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Gerrit-Change-Number: 59934 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3
by Sridhar Siricilla (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59362 ) Change subject: soc/intel/alderlake: Enable CPPCv3 ...................................................................... Patch Set 8: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59362/comment/713e89cd_f5eab72e PS7, Line 7: the helper functions > `Define CPPCv3 hybrid helper functions` Ack https://review.coreboot.org/c/coreboot/+/59362/comment/73f1ee34_787a5d40 PS7, Line 9: defines following > `defines the following` Ack https://review.coreboot.org/c/coreboot/+/59362/comment/16f3c977_5d98458c PS7, Line 12: TRUE > `true` Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Gerrit-Change-Number: 59362 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 20:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021