coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree
by Shon Wang (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Kevin Chiu, Wisley Chen, Shon Wang. Shon Wang has uploaded a new patch set (#10) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59304 ) Change subject: mb/google/brya/var/vell: update overridetree ...................................................................... mb/google/brya/var/vell: update overridetree Init basic override devicetree based on schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/vell/overridetree.cb 2 files changed, 367 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/59304/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/59304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa910eb1c5584197907963781258035c668298e Gerrit-Change-Number: 59304 Gerrit-PatchSet: 10 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree
by Shon Wang (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Kevin Chiu, Wisley Chen, Shon Wang. Shon Wang has uploaded a new patch set (#9) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59304 ) Change subject: mb/google/brya/var/vell: update overridetree ...................................................................... mb/google/brya/var/vell: update overridetree Init basic override devicetree based on schematice BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/vell/overridetree.cb 2 files changed, 367 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/59304/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa910eb1c5584197907963781258035c668298e Gerrit-Change-Number: 59304 Gerrit-PatchSet: 9 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: get SKU ID from EC (CBI)
by Rex-BC Chen (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59944 ) Change subject: mb/google/corsola: get SKU ID from EC (CBI) ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59944/comment/5bd44218_f979c851 PS5, Line 9: Retrieve the SKU ID for Corsola via CBI interface. > SKU ID is retrieved from Chrome EC on corsola. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Gerrit-Change-Number: 59944 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 08 Dec 2021 01:19:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: revise GPIO set of NOR flash for kingler/krabby
by Rex-BC Chen (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59945 ) Change subject: mb/google/corsola: revise GPIO set of NOR flash for kingler/krabby ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59945/comment/5aa127a6_8985c618 PS5, Line 7: for kingler/krabby > mark as unresolved. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Gerrit-Change-Number: 59945 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 08 Dec 2021 01:19:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/pi/Kconfig: select NO_SMM
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59810 ) Change subject: cpu/amd/pi/Kconfig: select NO_SMM ...................................................................... cpu/amd/pi/Kconfig: select NO_SMM Disable SMM_ASEG and select NO_SMM since the platforms do not use SMM. TEST=Boot Debian 11 on PC Engines apu3 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I47237421c3dd5bd043447831263d72c9956cdaf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59810 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/cpu/amd/pi/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Michał Żygowski: Looks good to me, approved diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index aff8d7dc..2336d68 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -10,7 +10,7 @@ select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select SMM_ASEG + select NO_SMM select SSE2 if CPU_AMD_PI -- To view, visit https://review.coreboot.org/c/coreboot/+/59810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47237421c3dd5bd043447831263d72c9956cdaf4 Gerrit-Change-Number: 59810 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Hung-Te Lin (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59955 ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4173f3cb646839ad12c4e43e8c50b0be53364f04 Gerrit-Change-Number: 59955 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 01:04:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Michał Żygowski, Frans Hendriks, Angel Pons, Arthur Heymans, Wim Vervoorn. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59754 ) Change subject: mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEM ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/mainboard/facebook/fbg1701/romstage.c: https://review.coreboot.org/c/coreboot/+/59754/comment/dd08252d_09b64b7e PS3, Line 21: u8 spd_index; : : switch (cpld_read_pcb_version()) { : case 0: /* intentional fallthrough */ : case 1: /* intentional fallthrough */ : case 2: /* intentional fallthrough */ : case 3: /* intentional fallthrough */ : case 4: /* intentional fallthrough */ : case 5: : spd_index = 0; : break; : case 6: /* intentional fallthrough */ : case 7: : spd_index = 1; : break; : default: : spd_index = 2; : break; : } > Idea: Put the switch block in a helper function: […] keeping this as it is right now and factoring out this code in a separate static function wouldn't be much of a difference for me, so i'd be ok with either way -- To view, visit https://review.coreboot.org/c/coreboot/+/59754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Gerrit-Change-Number: 59754 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 00:56:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Fix log2_ceil() for 0xffffffff
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59834 ) Change subject: lib: Fix log2_ceil() for 0xffffffff ...................................................................... lib: Fix log2_ceil() for 0xffffffff Current log2_ceil(x) is defined as log2(x * 2 - 1). When x is larger than (1 << 31), (x * 2 - 1) won't fit in u32, leading to incorrect result. Therefore, correct it as (log2(x - 1) + 1). Also add unit tests for inline functions in lib.h. BUG=none TEST=make tests/lib/lib-test BRANCH=none Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59834 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/include/lib.h M tests/lib/Makefile.inc A tests/lib/lib-test.c 3 files changed, 65 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved diff --git a/src/include/lib.h b/src/include/lib.h index 8e8bab5..b3cedb5 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -54,8 +54,8 @@ /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } -/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ -static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2_ceil(5) == 3 */ +static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x - 1) + 1; } static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } static inline int clz64(u64 x) { return x ? __builtin_clzll(x) : sizeof(x) * 8; } diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 0aea0ce..9a62476 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only +tests-y += lib-test tests-y += string-test tests-y += b64_decode-test tests-y += hexstrtobin-test @@ -40,6 +41,8 @@ tests-y += cbfs-lookup-has-mcache-test tests-y += lzma-test +lib-test-srcs += tests/lib/lib-test.c + string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c diff --git a/tests/lib/lib-test.c b/tests/lib/lib-test.c new file mode 100644 index 0000000..adaa2f9 --- /dev/null +++ b/tests/lib/lib-test.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <lib.h> +#include <tests/test.h> + +void test_popcnt(void **state) +{ + assert_int_equal(popcnt(0x0), 0); + assert_int_equal(popcnt(0x10), 1); + assert_int_equal(popcnt(0x10010010), 3); + assert_int_equal(popcnt(0xffffffff), 32); +} + +void test_clz(void **state) +{ + assert_int_equal(clz(0x0), 32); + assert_int_equal(clz(0xf), 28); + assert_int_equal(clz(0x80000000), 0); + assert_int_equal(clz(0xffffffff), 0); +} + +void test_log2(void **state) +{ + assert_int_equal(log2(0x0), -1); + assert_int_equal(log2(0x1), 0); + assert_int_equal(log2(0x5), 2); + assert_int_equal(log2(0x80000000), 31); + assert_int_equal(log2(0xffffffff), 31); +} + +void test_ffs(void **state) +{ + assert_int_equal(__ffs(0x0), -1); + assert_int_equal(__ffs(0x1), 0); + assert_int_equal(__ffs(0x1010), 4); + assert_int_equal(__ffs(0x10000000), 28); + assert_int_equal(__ffs(0xffffffff), 0); +} + +void test_log2_ceil(void **state) +{ + assert_int_equal(log2_ceil(0x0), -1); + assert_int_equal(log2_ceil(0x1), 0); + assert_int_equal(log2_ceil(0x5), 3); + assert_int_equal(log2_ceil(0x80000000), 31); + assert_int_equal(log2_ceil(0xffffffff), 32); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_popcnt), + cmocka_unit_test(test_clz), + cmocka_unit_test(test_log2), + cmocka_unit_test(test_ffs), + cmocka_unit_test(test_log2_ceil), + }; + + return cb_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e Gerrit-Change-Number: 59834 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59922 ) Change subject: mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init ...................................................................... mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/verstage.c M src/soc/amd/common/psp_verstage/psp_verstage.c 5 files changed, 85 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 5d3e21f..45b9e1d 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -311,25 +311,43 @@ return gpio_sleep_table; } -static const struct soc_amd_gpio early_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +static const struct soc_amd_gpio espi_gpio_table[] = { /* PCIE_RST0_L - Fixed timings */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { /* UART0_RXD - DEBUG */ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* UART0_TXD - DEBUG */ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_11, PULL_NONE), }; const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 415c426..7220c38 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -360,25 +360,43 @@ return gpio_sleep_table; } -static const struct soc_amd_gpio early_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +static const struct soc_amd_gpio espi_gpio_table[] = { /* PCIE_RST0_L - Fixed timings */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { /* UART0_RXD - DEBUG */ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* UART0_TXD - DEBUG */ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_130, PULL_NONE), }; const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 3f7e5d1..38c5d4a 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -33,6 +33,12 @@ */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + void variant_updm_update(FSP_M_CONFIG *mcfg); /* Program any required GPIOs at the finalize phase */ diff --git a/src/mainboard/google/zork/verstage.c b/src/mainboard/google/zork/verstage.c index e1277f4..0603257 100644 --- a/src/mainboard/google/zork/verstage.c +++ b/src/mainboard/google/zork/verstage.c @@ -2,6 +2,7 @@ #include <amdblocks/gpio.h> #include <baseboard/variants.h> +#include <psp_verstage.h> #include <security/vboot/vboot_common.h> static void setup_gpio(void) @@ -19,3 +20,27 @@ { setup_gpio(); } + +void verstage_mainboard_espi_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 2e3d09d..05c14d6 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -25,9 +25,6 @@ extern char _bss_start, _bss_end; -void __weak verstage_mainboard_early_init(void) {} -void __weak verstage_mainboard_espi_init(void) {} -void __weak verstage_mainboard_tpm_init(void) {} void __weak verstage_mainboard_init(void) {} uint32_t __weak get_max_workbuf_size(uint32_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/59922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Gerrit-Change-Number: 59922 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Subrata Banik, Wonkyu Kim, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59744 ) Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... Patch Set 7: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/59744/comment/42b9f98a_d6266661 PS7, Line 36: default n without having verified if that works, i wonder if "default y if !PLATFORM_USES_FSP2_X86_64" would be a better option that keeps the default, but still allows SoCs to select PLATFORM_USES_FSP2_X86_64 and override it -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 00:50:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021