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Change subject: mb/google/brya/variants/taniks: Configure GPIOs according to schematics
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/google/brya/variants/taniks/gpio.c:
https://review.coreboot.org/c/coreboot/+/59938/comment/f5af46df_28d27cc8
PS3, Line 95: /* F22 : VNN_CTRL ==> VNN_CTRL */
: PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
: /* F23 : BP105_CTRL ==> PP1050_CTRL */
: PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
> Just to clarify, taniks does have the VNN and PP1050 bypass rails?
Yes,taniks has the byapss rails too.
https://review.coreboot.org/c/coreboot/+/59938/comment/9a43c77d_9b50c559
PS3, Line 199:
> I also recommend deasserting SSD_PERST_L in the romstage GPIO table
Updated in latest patch
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Change subject: mb/google/brya/variants/taniks: Configure GPIOs according to schematics
......................................................................
mb/google/brya/variants/taniks: Configure GPIOs according to schematics
Update initial gpio configuration for taniks
BUG=b:209492408
TEST=FW_NAME=taniks emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab
---
A src/mainboard/google/brya/variants/taniks/Makefile.inc
A src/mainboard/google/brya/variants/taniks/gpio.c
2 files changed, 226 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59938/4
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Change subject: mb/intel/adlrvp_n: Add initial code for adl-n variant board
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
Generally looks good to me but I don't have any information for adlrvp-n board, so +1.
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Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Please fix compile errors.
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type
......................................................................
soc/intel/alderlake, soc/common: Add method to determine the cpu type
set_cpu_type(): It determines the CPU type (big or small) that
is executing the function, and marks the global_cpu_type's array slot
which is corresponds to the executing CPU's index if the CPU type is
big core.
get_cpu_index(): It determines the index from LAPIC Ids. This is
required to expose CPPC3 package in ascending order of CPUs' LAPIC ids.
So, the function returns CPU's position from the ascending order list
of LAPIC ids.
get_soc_cpu_type(): It returns the type of CPU that executing the
function.
Also, it calls the set_cpu_type() from soc/alderlake/cpu.c file.
TEST=Tested CPU index calculation, core type determination on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/Makefile.inc
A src/soc/intel/common/block/acpi/cpu_hybrid.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
5 files changed, 105 insertions(+), 0 deletions(-)
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Change subject: mb/google/corsola: get SKU ID from EC (CBI)
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59944/comment/9d7a42a9_674a9c28
PS5, Line 9: Retrieve the SKU ID for Corsola via CBI interface.
> Done
And the low/high value will be merged as one value.
please refer this code:
https://review.coreboot.org/c/coreboot/+/59944/6/src/mainboard/google/corso…
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Change subject: drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59869/comment/6986f162_4d9e9725
PS4, Line 10: IPU driver
> IPU kernel driver
Done
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/59869/comment/9338b816_43ba1cec
PS4, Line 335: Enables support for ES silicon ACPI entry for IPU.
> What is ES silicon? Please elabobrate? […]
ES is engineering silicon. I have updated the comment.
This is specific to alterlake and a temporary change, which will be removed.
I have raised following partner bug for the removal of this config.
https://partnerissuetracker.corp.google.com/issues/209663612
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I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info
......................................................................
drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info
Add entry in ACPI table under IPU device to provide silicon type
information to IPU driver. IPU kernel driver can decide the type of
firmware to load based on this information.
BUG=b:207721978
BRANCH=none
TEST=Check for the ACPI entry in the SSDT after booting to kernel
Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f
Cq-Depend: chromium:3319905
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/intel/mipi_camera/camera.c
M src/soc/intel/alderlake/Kconfig
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59869/5
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