coreboot-gerrit December 2021

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Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59929 ) Change subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59929/comment/58404c96_b8da25a0 PS1, Line 13: > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only this line seems to be a bit too long. same for line 24 -- To view, visit https://review.coreboot.org/c/coreboot/+/59929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Gerrit-Change-Number: 59929 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 00:43:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59928 ) Change subject: soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 Gerrit-Change-Number: 59928 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 00:40:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59933 ) Change subject: soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: CB:59968 will eventually remove this code, but i'd say that it might still be a good idea to first fix this and later remove the code in a separate commit -- To view, visit https://review.coreboot.org/c/coreboot/+/59933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Gerrit-Change-Number: 59933 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 00:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: use common fch_spi_early_init
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59968 ) Change subject: soc/amd/stoneyridge: use common fch_spi_early_init ...................................................................... soc/amd/stoneyridge: use common fch_spi_early_init All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c --- M src/mainboard/google/kahlee/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 3 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/59968/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 9b456c8..0ee9b58 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -25,32 +25,6 @@ void bootblock_mainboard_init(void) { - if (CONFIG(EM100)) { - /* - * We should be able to rely on defaults, but it seems safer - * to explicitly set up these registers. - */ - sb_read_mode(SPI_READ_MODE_NOM); - sb_set_spi100(SPI_SPEED_16M, /* Normal */ - SPI_SPEED_16M, /* Fast */ - SPI_SPEED_16M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ - } else { - /* - * W25Q128FW Setup - * Normal Read 40MHz - * Fast Read 104MHz - * Dual Read IO (1-2-2) - */ - sb_read_mode(SPI_READ_MODE_DUAL122); - - /* Set SPI speeds before verstage. Needed for TPM */ - sb_set_spi100(SPI_SPEED_33M, /* Normal */ - SPI_SPEED_66M, /* Fast */ - SPI_SPEED_66M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ - } - /* Setup TPM decode before verstage */ lpc_tpm_decode_spi(); } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 74e9498..2773751 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -142,41 +142,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -#define SPI_CNTRL0 0x00 -#define SPI_BUSY BIT(31) -#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -/* Nominal is 16.7MHz on older devices, 33MHz on newer */ -#define SPI_READ_MODE_NOM 0x00000000 -#define SPI_READ_MODE_DUAL112 ( BIT(29) ) -#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) -#define SPI_READ_MODE_DUAL122 (BIT(30) ) -#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) -#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) -#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) -#define SPI_ACCESS_MAC_ROM_EN BIT(22) -#define SPI_FIFO_PTR_CLR BIT(20) -#define SPI_ARB_ENABLE BIT(19) -#define EXEC_OPCODE BIT(16) - -#define SPI100_ENABLE 0x20 -#define SPI_USE_SPI100 BIT(0) - -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ -#define SPI100_SPEED_CONFIG 0x22 -#define SPI_SPEED_66M (0x0) -#define SPI_SPEED_33M ( BIT(0)) -#define SPI_SPEED_22M ( BIT(1) ) -#define SPI_SPEED_16M ( BIT(1) | BIT(0)) -#define SPI_SPEED_100M (BIT(2) ) -#define SPI_SPEED_800K (BIT(2) | BIT(0)) -#define SPI_NORM_SPEED_NEW_SH 12 -#define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 -#define SPI_TPM_SPEED_NEW_SH 0 - -#define SPI100_HOST_PREF_CONFIG 0x2c -#define SPI_RD4DW_EN_HOST BIT(15) - /* Platform Security Processor D8F0 */ void soc_enable_psp_early(void); @@ -219,8 +184,6 @@ void enable_aoac_devices(void); void fch_clk_output_48Mhz(u32 osc); -void sb_read_mode(u32 mode); -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); /* * Call the mainboard to get the USB Over Current Map. The mainboard diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 3b2cba6..2ffbc92 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -227,35 +227,6 @@ misc_write32(MISC_CLK_CNTL1, ctrl); } -static void sb_init_spi_base(void) -{ - /* Make sure the base address is predictable */ - lpc_set_spibase(SPI_BASE_ADDRESS); - lpc_enable_spi_rom(SPI_ROM_ENABLE); -} - -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) -{ - spi_write16(SPI100_SPEED_CONFIG, - (norm << SPI_NORM_SPEED_NEW_SH) | - (fast << SPI_FAST_SPEED_NEW_SH) | - (alt << SPI_ALT_SPEED_NEW_SH) | - (tpm << SPI_TPM_SPEED_NEW_SH)); - spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE)); -} - -static void sb_disable_4dw_burst(void) -{ - spi_write16(SPI100_HOST_PREF_CONFIG, - spi_read16(SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); -} - -void sb_read_mode(u32 mode) -{ - spi_write32(SPI_CNTRL0, - (spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); -} - static void setup_spread_spectrum(int *reboot) { uint16_t rstcfg = pm_read16(PWR_RESET_CFG); @@ -334,9 +305,9 @@ sb_enable_lpc(); lpc_enable_port80(); sb_lpc_decode(); - lpc_enable_spi_prefetch(); - sb_init_spi_base(); - sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ + /* Make sure the base address is predictable */ + lpc_set_spibase(SPI_BASE_ADDRESS); + fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io(); setup_spread_spectrum(&reboot); -- To view, visit https://review.coreboot.org/c/coreboot/+/59968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Gerrit-Change-Number: 59968 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kahlee/Kconfig: add remaining SPI speed settings
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59967 ) Change subject: mb/google/kahlee/Kconfig: add remaining SPI speed settings ...................................................................... mb/google/kahlee/Kconfig: add remaining SPI speed settings Before this patch only the SPI settings that will also end up in the amdfw part of the firmware were specified in the board's Kconfig. This patch adds the settings from Kahlee's bootblock.c to the Kconfig file which will be needed in subsequent patches. Also add a comment about the EM100 case. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie42feb9b41f435c329bf1c78471e65ef5a3fb783 --- M src/mainboard/google/kahlee/Kconfig 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59967/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 29edb30..c82a20e 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -123,12 +123,22 @@ depends on USE_OEM_BIN default "" -if !EM100 +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 4 # Dual IO (1-2-2) config EFS_SPI_SPEED default 0 # 66MHz + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 0 # 66MHz + +config TPM_SPI_SPEED + default 0 # 66MHz + endif # Don't use AMD's Secure OS -- To view, visit https://review.coreboot.org/c/coreboot/+/59967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42feb9b41f435c329bf1c78471e65ef5a3fb783 Gerrit-Change-Number: 59967 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59966 ) Change subject: soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2 ...................................................................... soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2 The PSP EFS code to get the SPI mode and speed from the amdfw part of the firmware image also works for Stoneyridge which is the one SoC that selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already handles the SOC_AMD_STONEYRIDGE case. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986 --- M src/soc/amd/common/block/psp/Makefile.inc 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59966/1 diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 2b407a2..94dc57c 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -5,6 +5,9 @@ smm-y += psp.c smm-y += psp_smm.c +bootblock-y += psp_efs.c +verstage-y += psp_efs.c + endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) @@ -22,7 +25,4 @@ smm-y += psp_gen2.c smm-y += psp_smm_gen2.c -bootblock-y += psp_efs.c -verstage-y += psp_efs.c - endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986 Gerrit-Change-Number: 59966 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: use KiB and MiB definitions
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59936 ) Change subject: soc/amd: use KiB and MiB definitions ...................................................................... soc/amd: use KiB and MiB definitions Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/agesa_acpi.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index b6e4ac2..8628096 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -14,7 +14,7 @@ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, 0x44); - res->size = 512 * 1024; + res->size = 512 * KiB; res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffff; /* 4G */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 7c46645..ebded6b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -106,7 +106,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / KiB, 1, IORESOURCE_SUBTRACTIVE); res = new_resource(dev, 3); /* IOAPIC */ diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 7826007..4ab31e5 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -82,7 +82,7 @@ if (memory_base == 0) { current = create_crat_memory_entry(0, 0ull, 0xa0000ull, current); - memory_base = (1 * 1024 * 1024); + memory_base = 1 * MiB; memory_length = memory_base; new_entries++; } -- To view, visit https://review.coreboot.org/c/coreboot/+/59936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Gerrit-Change-Number: 59936 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/*: Enable measured boot
by Tim Crawford (Code Review) 07 Dec '21

07 Dec '21

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59963 ) Change subject: mb/system76/*: Enable measured boot ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d Gerrit-Change-Number: 59963 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Dec 2021 23:53:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation
by Tim Wawrzynczak (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59949 ) Change subject: mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59949/comment/3a0b352b_90b648ff PS1, Line 10: - Set slow slew rate VCCIA and VCCGT to 16 > Hi Paul, […] Maybe change commit msg to `Copied from gimble` -- To view, visit https://review.coreboot.org/c/coreboot/+/59949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb Gerrit-Change-Number: 59949 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Dec 2021 22:55:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/taniks: Configure GPIOs according to schematics
by Tim Wawrzynczak (Code Review) 07 Dec '21

07 Dec '21

Attention is currently required from: YH Lin, Joey Peng, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59938 ) Change subject: mb/google/brya/variants/taniks: Configure GPIOs according to schematics ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/variants/taniks/gpio.c: https://review.coreboot.org/c/coreboot/+/59938/comment/a577d4e9_e62f422f PS3, Line 95: /* F22 : VNN_CTRL ==> VNN_CTRL */ : PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), : /* F23 : BP105_CTRL ==> PP1050_CTRL */ : PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), Just to clarify, taniks does have the VNN and PP1050 bypass rails? https://review.coreboot.org/c/coreboot/+/59938/comment/27747480_d5100271 PS3, Line 199: I also recommend deasserting SSD_PERST_L in the romstage GPIO table -- To view, visit https://review.coreboot.org/c/coreboot/+/59938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab Gerrit-Change-Number: 59938 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 07 Dec 2021 22:54:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021