coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kco...
by Joey Peng (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: YH Lin, Tim Wawrzynczak. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60022 ) Change subject: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Hi Tim and YH, yes, we have seen that CL but seems that the CL has some issues. […] Hi google team, I verified with 14394 and this issue can't duplicate on taeko. We will keep monitor and abandon this change first. -- To view, visit https://review.coreboot.org/c/coreboot/+/60022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic58f8fee87559f2d5ad107ca3c9da882e4eb2381 Gerrit-Change-Number: 60022 Gerrit-PatchSet: 4 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 13 Dec 2021 03:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: YH Lin <yueherngl(a)google.com> Comment-In-Reply-To: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add __fls() (Find Last Set)
by Hung-Te Lin (Code Review) 13 Dec '21

13 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59738 ) Change subject: lib: Add __fls() (Find Last Set) ...................................................................... lib: Add __fls() (Find Last Set) Implement __fls() as an alias for log2(), and remove the duplicate definitions in commonlib/storage/sdhci.c. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M payloads/libpayload/include/libpayload.h M src/commonlib/storage/sdhci.c M src/include/lib.h M tests/lib/lib-test.c 4 files changed, 19 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index e08d211..3895710 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -457,6 +457,8 @@ static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } +/* Find Last Set: __fls(1) == 0, __fls(5) == 2, __fls(1 << 31) == 31 */ +static inline int __fls(u32 x) { return log2(x); } static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } static inline int clz64(u64 x) @@ -466,6 +468,7 @@ static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } +static inline int __fls64(u64 x) { return log2_64(x); } /** @} */ /** diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 6d39a45..16420d9 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -6,14 +6,15 @@ #include "bouncebuf.h" #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> +#include <commonlib/stdlib.h> #include <commonlib/storage.h> #include <delay.h> #include <endian.h> +#include <lib.h> #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" #include <timer.h> -#include <commonlib/stdlib.h> #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_SEPARATE_VERSTAGE) \ @@ -411,36 +412,6 @@ return 0; } -/* Find leftmost set bit in a 32 bit integer */ -static int fls(u32 x) -{ - int r = 32; - - if (!x) - return 0; - if (!(x & 0xffff0000u)) { - x <<= 16; - r -= 16; - } - if (!(x & 0xff000000u)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf0000000u)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc0000000u)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x80000000u)) { - x <<= 1; - r -= 1; - } - return r; -} - static void sdhci_set_power(struct sdhci_ctrlr *sdhci_ctrlr, unsigned short power) { @@ -718,7 +689,7 @@ if (rv) return rv; /* The error has been already reported */ - sdhci_set_power(sdhci_ctrlr, fls(ctrlr->voltages) - 1); + sdhci_set_power(sdhci_ctrlr, __fls(ctrlr->voltages)); if (ctrlr->caps & DRVR_CAP_NO_CD) { unsigned int status; diff --git a/src/include/lib.h b/src/include/lib.h index b3cedb5..863888e 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -53,6 +53,8 @@ static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } +/* Find Last Set: __fls(1) == 0, __fls(5) == 2, __fls(1 << 31) == 31 */ +static inline int __fls(u32 x) { return log2(x); } /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2_ceil(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x - 1) + 1; } @@ -61,5 +63,6 @@ static inline int clz64(u64 x) { return x ? __builtin_clzll(x) : sizeof(x) * 8; } static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } +static inline int __fls64(u64 x) { return log2_64(x); } #endif /* __LIB_H__ */ diff --git a/tests/lib/lib-test.c b/tests/lib/lib-test.c index adaa2f9..826c6c5 100644 --- a/tests/lib/lib-test.c +++ b/tests/lib/lib-test.c @@ -37,6 +37,15 @@ assert_int_equal(__ffs(0xffffffff), 0); } +void test_fls(void **state) +{ + assert_int_equal(__fls(0x0), -1); + assert_int_equal(__fls(0x1), 0); + assert_int_equal(__fls(0x5), 2); + assert_int_equal(__fls(0x80000000), 31); + assert_int_equal(__fls(0xffffffff), 31); +} + void test_log2_ceil(void **state) { assert_int_equal(log2_ceil(0x0), -1); @@ -53,6 +62,7 @@ cmocka_unit_test(test_clz), cmocka_unit_test(test_log2), cmocka_unit_test(test_ffs), + cmocka_unit_test(test_fls), cmocka_unit_test(test_log2_ceil), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Gerrit-Change-Number: 59738 Gerrit-PatchSet: 7 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus: Configure Acoustic noise mitigation
by Casper Chang (Code Review) 13 Dec '21

13 Dec '21

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60071 ) Change subject: mb/google/brya/var/primus: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/primus: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 BUG=b:204844399 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/60071/1 diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index ef5ad98..58c52a7 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -35,6 +35,12 @@ register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index ce06d30..22d61b0 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -35,6 +35,12 @@ register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/60071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Gerrit-Change-Number: 60071 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Robert Chen (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Kevin Chiu, YH Lin, Tim Wawrzynczak, Nick Vaccaro, Robert Chen, Patrick Rudolph. Robert Chen has uploaded a new patch set (#15) to the change originally created by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... mb/google/brya/var/vell: update memory settings DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3 GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7 GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5 BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> --- A src/mainboard/google/brya/variants/vell/memory.c 1 file changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59334/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 15 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/vell: update gpio override
by Robert Chen (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Kevin Chiu, Robert Chen, Nick Vaccaro, Wisley Chen. Robert Chen has uploaded a new patch set (#19) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59305 ) Change subject: mb/google/brya/var/vell: update gpio override ...................................................................... mb/google/brya/var/vell: update gpio override Configure GPIOs according to schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- A src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/gpio.c 2 files changed, 182 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59305/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/59305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Gerrit-Change-Number: 59305 Gerrit-PatchSet: 19 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taeko: Fix PLD group order (W/A)
by Kevin Chang (Code Review) 13 Dec '21

13 Dec '21

Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59973 ) Change subject: mb/google/brya/var/taeko: Fix PLD group order (W/A) ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > So why is this a workaround? Because on "Taeko" HW design should be port 3 not port 2, but if set ACPI group with ACPI_PLD_GROUP(3, 1) system will always reboot, according to Tim reply in issue tracker this is cause by kernel CL, so this is workaround in coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/59973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b Gerrit-Change-Number: 59973 Gerrit-PatchSet: 8 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 13 Dec 2021 02:46:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: set up open-drain ChromeOS pins
by Rex-BC Chen (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60002 ) Change subject: mb/google/corsola: set up open-drain ChromeOS pins ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: hi @yu-ping, any suggetion for this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/60002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Gerrit-Change-Number: 60002 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 13 Dec 2021 02:08:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: add tracker dump
by Rex-BC Chen (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59990 ) Change subject: soc/mediatek/mt8186: add tracker dump ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: hi @yu-ping, any suggetion for this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/59990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 Gerrit-Change-Number: 59990 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 13 Dec 2021 02:08:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: add support for tracker version one
by Rex-BC Chen (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59989 ) Change subject: soc/mediatek: add support for tracker version one ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: hi @yu-ping, any suggetion for this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/59989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Gerrit-Change-Number: 59989 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 13 Dec 2021 02:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kco...
by Joey Peng (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: YH Lin, Tim Wawrzynczak. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60022 ) Change subject: mb/google/brya/var/taeko: Add define SOC_INTEL_ALDERLAKE_PCH_P in Kconfig.name ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > I can confirm "CONFIG_SOC_INTEL_ALDERLAKE_PCH_P=y" is already in the Taeko's config. Hi Tim and YH, yes, we have seen that CL but seems that the CL has some issues. Please see the issue tracker for more details. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/60022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic58f8fee87559f2d5ad107ca3c9da882e4eb2381 Gerrit-Change-Number: 60022 Gerrit-PatchSet: 4 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 13 Dec 2021 01:22:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: YH Lin <yueherngl(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit December 2021