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Change subject: soc/amd/stoneyridge: split southbridge code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/stoneyridge/fch.c:
https://review.coreboot.org/c/coreboot/+/60142/comment/b24621bd_a8ef4534
PS1, Line 175: if (gnvs) {
There's probably no need to have them in GNVS or update on S3 resume path.
So xHCI has to reload firmware from SPI flash on D0 transition?
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Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
......................................................................
Patch Set 7:
(5 comments)
File src/mainboard/intel/adlrvp/gpio_n.c:
https://review.coreboot.org/c/coreboot/+/59937/comment/ce6549ce_9d51fcef
PS6, Line 147:
> nit: extra line
Ack
https://review.coreboot.org/c/coreboot/+/59937/comment/5d2ad740_d5c0f88b
PS6, Line 158:
> nit: extra line
Ack
https://review.coreboot.org/c/coreboot/+/59937/comment/905e3303_16e61f3f
PS6, Line 164:
> nit: extra line
Ack
https://review.coreboot.org/c/coreboot/+/59937/comment/0282fca3_a399005b
PS6, Line 180:
> nit: extra line
Ack
https://review.coreboot.org/c/coreboot/+/59937/comment/19ad9d43_35d765b4
PS6, Line 184:
> nit: extra line
Ack
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Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/intel/adlrvp/gpio_n.c:
https://review.coreboot.org/c/coreboot/+/59937/comment/996f1745_c484c916
PS5, Line 52: /*TCP1_DISP_AUX_P_BIAS_GPIO*/
: PAD_CFG_GPO(GPP_E20, 1, PLTRST),
: /*TCP1_DISP_AUX_N_BIAS_GPIO*/
: PAD_CFG_GPO(GPP_E21, 0, PLTRST),
: /*TCP0_DISP_AUX_P_BIAS_GPIO*/
: PAD_CFG_GPO(GPP_E22, 0, PLTRST),
: /*TCP0_DISP_AUX_N_BIAS_GPIO*/
: PAD_CFG_GPO(GPP_E23, 1, PLTRST),
> I am guessing here from the pad names, but should these be NF6 for AUX BIAS functionality?
These are GPIO pins used for providing BIAS functionality to the AUX lines. We will configure them based on the orientation of the display device plugged on Type-C.
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Hello build bot (Jenkins), Hsuan Ting Chen, Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: coreboot-sdk/Dockerfile: Build and install libflashrom
......................................................................
coreboot-sdk/Dockerfile: Build and install libflashrom
By updating vboot submodule to ToT in commit 18437a7b (Update vboot
submodule to upstream master), crrev.com/c/3247852
(vboot_reference/futility: Port W path to using libflashrom) will be
included as well.
The vboot CL added a dependency of libflashrom because it included
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Add the dependency of cloning from flashrom repository, making
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Change-Id: I7269a5140fb02da6d143b339116db2fd089f8da8
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
---
M util/docker/coreboot-sdk/Dockerfile
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60095/3
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Gwendal Grignou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59609 )
Change subject: mb/google/dedede/var/bugzzy: Add SAR sensor
......................................................................
Patch Set 5:
(6 comments)
File src/mainboard/google/dedede/variants/bugzzy/gpio.c:
https://review.coreboot.org/c/coreboot/+/59609/comment/d4a3f074_3257b86c
PS3, Line 51: /* E11 : WIFI_SAR_SENSOR_INT */
: PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE),
> We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tre […]
Done
File src/mainboard/google/dedede/variants/bugzzy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59609/comment/5911b190_ca4f9f17
PS3, Line 51: [PchSerialIoIndexI2C5] = PchSerialIoPci,
> We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tre […]
Done
https://review.coreboot.org/c/coreboot/+/59609/comment/fff1991a_1f07b6b6
PS3, Line 67: #| I2C5 | P-sensor(Wifi) |
> We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tre […]
Done
https://review.coreboot.org/c/coreboot/+/59609/comment/38ed1f0a_fe4a590b
PS3, Line 231: device i2c 28 on end
> Can we add this as well: […]
Done
https://review.coreboot.org/c/coreboot/+/59609/comment/5a2fbde6_1ce54d77
PS3, Line 239: #register "generic.probed" = "1"
> We don't need it.
Done
https://review.coreboot.org/c/coreboot/+/59609/comment/ef5b61a3_7e901825
PS3, Line 338: device pci 19.1 on
: chip drivers/i2c/sx9360
: register "desc" = ""SAR Proximity Sensor - Wifi""
: register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
: register "uid" = "2"
: register "proxraw_strength" = "2"
: register "avg_pos_strength" = "16"
: register "resolution" = "1024"
: device i2c 28 on end
: end
: end #I2C 5
> We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tre […]
Done
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Change subject: driver/i2c: Add sx9360 driver
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59608/comment/2fd49d2d_50b6729b
PS3, Line 12: Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
> That’s not yet in Linus’ master branch?
It was presumptive: the patch has been submitted only:
https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985…
File src/drivers/i2c/sx9360/sx9360.c:
PS2:
> Good point. Please mention in the commit message, what code you took as base.
Done
https://review.coreboot.org/c/coreboot/+/59608/comment/21e6de1f_0524d99d
PS2, Line 15: REGISTER
> It is unused, I should have removed it when copied the code from sx9324.
Done
https://review.coreboot.org/c/coreboot/+/59608/comment/307790c7_3b505d2a
PS2, Line 61: describe
> described
Done
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Hello build bot (Jenkins), Paul Menzel, SH Kim, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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Change subject: driver/i2c: Add sx9360 driver
......................................................................
driver/i2c: Add sx9360 driver
Add driver for setting up Semtech sx9360 SAR sensor.
The driver is based on sx9310.c. The core of the driver is the same, but
the bindings are slightly different.
Registers are documented in the kernel tree:
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org>
Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516
---
A src/drivers/i2c/sx9360/Kconfig
A src/drivers/i2c/sx9360/Makefile.inc
A src/drivers/i2c/sx9360/chip.h
A src/drivers/i2c/sx9360/sx9360.c
4 files changed, 158 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59608/4
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Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
......................................................................
Patch Set 6:
(5 comments)
File src/mainboard/intel/adlrvp/gpio_n.c:
https://review.coreboot.org/c/coreboot/+/59937/comment/e235560b_ff7af6d9
PS6, Line 147:
nit: extra line
https://review.coreboot.org/c/coreboot/+/59937/comment/aff7e595_8df786f1
PS6, Line 158:
nit: extra line
https://review.coreboot.org/c/coreboot/+/59937/comment/4df4b39c_b0bdab7e
PS6, Line 164:
nit: extra line
https://review.coreboot.org/c/coreboot/+/59937/comment/6cbf6633_07e3c9ef
PS6, Line 180:
nit: extra line
https://review.coreboot.org/c/coreboot/+/59937/comment/71961025_f484bd82
PS6, Line 184:
nit: extra line
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Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60100/comment/6fffc78e_12aab3f0
PS2, Line 9: found that
> experienced?
Done
https://review.coreboot.org/c/coreboot/+/60100/comment/bf77a382_86314ec8
PS2, Line 10: cr50
: firmware to the 0.6.70.
> Was this firmware supposed to fix it?
No. I just apply the latest version but it is still not working.
https://review.coreboot.org/c/coreboot/+/60100/comment/3810de50_319f9460
PS2, Line 12: So, we submitted
: this patch to disable the gpio power management.
> Please describe the problem, and why this fix. […]
Done
File src/mainboard/google/brya/variants/brask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/60100/comment/82013762_12a57e2c
PS2, Line 2: disabled
> disables
Done
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