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Change subject: libpayload: Parse DDR Information through coreboot tables
......................................................................
libpayload: Parse DDR Information through coreboot tables
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
---
M payloads/libpayload/include/coreboot_tables.h
M payloads/libpayload/include/libpayload.h
A payloads/libpayload/include/mem_chip_info.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
5 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59193/7
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Change subject: Herobrine: sc7280: Add support for audio
......................................................................
Herobrine: sc7280: Add support for audio
Add gpio configuration for target specific i2s ports
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org>
Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002
---
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/herobrine/mainboard.c
3 files changed, 28 insertions(+), 0 deletions(-)
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Change subject: mb/google/herobrine: Initialize SPI FW for EC and TPM
......................................................................
mb/google/herobrine: Initialize SPI FW for EC and TPM
Initialize SPI firmware for EC and H1/TPM instances for Piglin and Hoglin.
Load QUP FW in respective Serial Engines.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c
Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org>
---
M src/mainboard/google/herobrine/Kconfig
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/bootblock.c
M src/mainboard/google/herobrine/chromeos.c
4 files changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/50581/93
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Change subject: mb/google/guybrush/var/nipperkin: config eSPI as dedicated alert
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60082/comment/efb086e7_96f80c07
PS2, Line 2: Author: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
> Use your company address? […]
Done
https://review.coreboot.org/c/coreboot/+/60082/comment/d450a1b0_03154f36
PS2, Line 8:
> What problem is fixed? Please summarize the bug reports.
Done
https://review.coreboot.org/c/coreboot/+/60082/comment/f053e76b_b0a1fbae
PS2, Line 12: DUT(6 units)
> Space before (.
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush/var/nipperkin: config eSPI as dedicated alert
......................................................................
mb/google/guybrush/var/nipperkin: config eSPI as dedicated alert
Setup eSPI to dedicated alert per the latest schematic changes.
DUT won't hang up at power on boot due to eSPI alert is triggerred
unexpectedly.
BUG=b:199458949,b:203446084
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
test power on/reboot on DUT (6 units) each 10 loops->pass
Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234
Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com>
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 0 insertions(+), 2 deletions(-)
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Change subject: commonlib: Add new TS for CSE firmware Sync
......................................................................
Patch Set 4:
(1 comment)
File src/commonlib/include/commonlib/timestamp_serialized.h:
https://review.coreboot.org/c/coreboot/+/59668/comment/31426bb9_e2fc7e5b
PS3, Line 141: TS_START_CSE_FW_SYNC = 972,
: TS_END_CSE_FW_SYNC = 973,
> Hm, ideally these would go between 940 and 950 but there's only 1 space left. […]
Ack
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Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync
......................................................................
soc/intel/alderlake: Add timestamp for cse_fw_sync
The patch add timestamp around cse_fw_sync().
TEST=Verified on Brya, cbmem -t:
948:starting CSE firmware sync 1,381,577 (45,227
949:finished CSE firmware sync 1,459,513 (77,936)
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 5 insertions(+), 1 deletion(-)
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Change subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60139/comment/959cd8b6_29d28208
PS1, Line 11: in verstage during s0i3 resume
Please add a dot/period at the end of sentences.
https://review.coreboot.org/c/coreboot/+/60139/comment/753a91b5_b52ab615
PS1, Line 12:
Why does the TPM need to be reinitialized? Why can’t the OS do it for example?
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