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Change subject: soc/intel/alderlake: Rename ADL_P_482_CORE to ADL_P_482_28W_CORE
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60267/comment/f03ee06f_5347bec4
PS1, Line 9: Every VR config items are not the same between ADL-P 4+8+2 28 & 45W.
The VR config items differ between ADL-P 4+8+2 28W and 45W. The current settings are for ADL-P 4+8+2 28W, so rename the enum member.
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Change subject: FSP 2511 headers include.
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60259/comment/54d0b4c6_067214e2
PS1, Line 7: Meminit function call in coreboot has been updated as per new FSP
: UPD and DQS in headers.
:
: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS &
: UPD calls.
: src/soc/intel/alderlake/fsp_params.c : Updated LpmStateEnableMask UPD
> Ack
The message summary still does not follow the common style. Please see how other FSP header commits are worded.
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Change subject: docker/Makefile: Use all instead of all_without_gdb
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60268/comment/f327a166_2bc56c8d
PS1, Line 10: it
What fails?
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Change subject: mb/google/brya: Add a new baseboard nissa
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60271/comment/82486638_31d7d9e5
PS2, Line 7: mb/google/brya: Add a new baseboard nissa
_ with variants nivviks and nereid
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Change subject: mb/starlabs/labtop: Enable I2C4
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60264/comment/022ea7e6_70669651
PS2, Line 7: mb/starlabs/labtop: Enable I2C4
Mayeb:
> Enable I2C4 to get UART2 working
https://review.coreboot.org/c/coreboot/+/60264/comment/95946deb_70a69255
PS2, Line 12:
How did you test UART2 is working?
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Change subject: coreboot-sdk/Dockerfile: Build and install libflashrom
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Set to WIP
This code is not correct yet; we did not generate the .pc file.
And currently we could only generate this pc file with meson build.
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Change subject: mainboard/starlabs: Add LabTop Mk IV
......................................................................
Patch Set 72:
(1 comment)
File src/mainboard/starlabs/labtop/variants/cml/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/58428/comment/2a782b45_9a3d767a
PS66, Line 125: device pci 19.0 off end # I2C4
> Haven't checked, but I think so.
Done
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Change subject: mb/starlabs/labtop: Enable I2C4
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60264/comment/8ae3156e_cb52f0ad
PS1, Line 9: Enable I2C4 to allow for proper enumeration but avoid FSP configuring it.
> nit: The period goes past the 72-char line length limit. […]
Done
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60264
to look at the new patch set (#2).
Change subject: mb/starlabs/labtop: Enable I2C4
......................................................................
mb/starlabs/labtop: Enable I2C4
Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be
enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from
configuring anything regarding I2C4 (e.g. GPIOs).
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd
---
M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/60264/2
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