coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/alderlake: Add timestamp for cse_fw_sync
by Tim Wawrzynczak (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60135 ) Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Gerrit-Change-Number: 60135 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 18:53:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Configure GPIO to release PERST# earlier
by Tim Wawrzynczak (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60279 ) Change subject: mb/google/brya/var/gimble: Configure GPIO to release PERST# earlier ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60279/comment/cfd7cc6e_8ba0871f PS1, Line 9: Improve power consumption of SDCard controller suggestion, to explain the situation a little better: ``` This change in power sequencing appears to fix issues with power consumption of the SD card controller. Possibly this change ensures the device has enough time to properly initialize itself after reset is deasserted but before it is accessed. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/60279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338 Gerrit-Change-Number: 60279 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Dec 2021 18:52:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Update Slow Slew Rate
by Tim Wawrzynczak (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60277 ) Change subject: mb/google/brya/var/gimble: Update Slow Slew Rate ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: what about gimble4es? -- To view, visit https://review.coreboot.org/c/coreboot/+/60277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711 Gerrit-Change-Number: 60277 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Dec 2021 18:20:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Tim Wawrzynczak (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Paul Menzel, Kenneth Chan, Rehan Ghori. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60131 ) Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 7 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-Comment-Date: Tue, 21 Dec 2021 18:17:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build ...
by Nico Huber (Code Review) 21 Dec '21

21 Dec '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51671 ) Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time ...................................................................... arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time According to util/kbc1126/README.md, for these ECs to work, the address and size of their two firmware should be written to $s-0x100` (`$s` means the image size, done with kbc1126_ec_insert), which means that every existing section (especially those used to store code) should not overlap this address, otherwise the bootblock will get damaged when inserting firmwares of the EC. In this commit, ecfw_ptr is a structure initialized at build time according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET (to do so, they should be redefined as hex), and linked to CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not needed at build time any more. Test passed on Elitebook Folio 9470m. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51671 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/Kconfig M src/arch/x86/bootblock.ld M src/ec/hp/kbc1126/Kconfig M src/ec/hp/kbc1126/Makefile.inc A src/ec/hp/kbc1126/ecfw_ptr.c A src/ec/hp/kbc1126/ecfw_ptr.h 6 files changed, 75 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6af3fa8..207654d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -340,4 +340,23 @@ string default "src/arch/x86/memlayout.ld" +# Some EC need an "EC firmware pointer" (a data structure hinting the address +# of its firmware blobs) being put at a fixed position. Its space +# (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a +# stage. Different EC may have different format and/or value for it. The actual +# address of EC firmware pointer should be provided in the Kconfig of the EC +# requiring it, and its value could be filled by linking a read-only global +# data object to the section above. + +config ECFW_PTR_ADDR + hex + help + Address of reserved space for EC firmware pointer, which should not + overlap other data such as reset vector or FIT pointer if present. + +config ECFW_PTR_SIZE + int + help + Size of reserved space for EC firmware pointer + endif diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 4ab2275..0b908bb 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -31,7 +31,7 @@ */ PROGRAM_SZ = SIZEOF(.text) + 512; - . = MIN(_ID_SECTION, _FIT_POINTER) - EARLYASM_SZ; + . = MIN(_ECFW_PTR, MIN(_ID_SECTION, _FIT_POINTER)) - EARLYASM_SZ; . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16); BOOTBLOCK_TOP = .; .init (.) : { @@ -56,6 +56,13 @@ _ID_SECTION_END = SIZEOF(.fit_pointer) && SIZEOF(.id) > 0x28 ? 0xffffff80 : _X86_RESET_VECTOR; _ID_SECTION = _ID_SECTION_END - SIZEOF(.id); + . = _ECFW_PTR; + .ecfw_ptr (.): { + ASSERT((SIZEOF(.ecfw_ptr) == CONFIG_ECFW_PTR_SIZE), "Size of ecfw_ptr is incorrect"); + KEEP(*(.ecfw_ptr)); + } + _ECFW_PTR = SIZEOF(.ecfw_ptr) ? CONFIG_ECFW_PTR_ADDR : _X86_RESET_VECTOR; + . = _FIT_POINTER; .fit_pointer (.): { KEEP(*(.fit_pointer)); diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index cb4ddec..5e6edd6 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -27,6 +27,12 @@ Select this option to add the two firmware blobs for KBC1126. You need these two blobs to power on your machine. +config ECFW_PTR_ADDR + default 0xffffff00 + +config ECFW_PTR_SIZE + default 8 + config KBC1126_FW1 string "KBC1126 firmware #1 path and filename" depends on KBC1126_FIRMWARE @@ -37,9 +43,9 @@ vendor firmware. config KBC1126_FW1_OFFSET - string "Offset of KBC1126 firmware #1" + hex "Offset of KBC1126 firmware #1" depends on KBC1126_FIRMWARE - default "0xfffe8000" + default 0xfffe8000 config KBC1126_FW2 string "KBC1126 filename #2 path and filename" @@ -51,8 +57,8 @@ vendor firmware. config KBC1126_FW2_OFFSET - string "Offset of KBC1126 firmware #2" + hex "Offset of KBC1126 firmware #2" depends on KBC1126_FIRMWARE - default "0xfffd0000" + default 0xfffd0000 endif diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index 4d7d46d..3f7fa19 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -1,7 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS),y) -KBC1126_EC_INSERT:=$(top)/util/kbc1126/kbc1126_ec_insert + +bootblock-y += ecfw_ptr.c ifeq ($(CONFIG_KBC1126_FIRMWARE),y) cbfs-files-y += ecfw1.bin @@ -16,15 +17,6 @@ ecfw2.bin-type := raw endif -$(call add_intermediate, kbc1126_ec_insert) -ifeq ($(CONFIG_KBC1126_FIRMWARE),y) - printf " Building kbc1126_ec_insert.\n" - $(MAKE) -C util/kbc1126 - printf " KBC1126 Inserting KBC1126 firmware blobs.\n" - $(KBC1126_EC_INSERT) $(obj)/coreboot.pre \ - $(CONFIG_KBC1126_FW1_OFFSET) $(CONFIG_KBC1126_FW2_OFFSET) -endif - build_complete:: ifeq ($(CONFIG_KBC1126_FIRMWARE),) printf "\n** WARNING **\n" diff --git a/src/ec/hp/kbc1126/ecfw_ptr.c b/src/ec/hp/kbc1126/ecfw_ptr.c new file mode 100644 index 0000000..8a29c6c --- /dev/null +++ b/src/ec/hp/kbc1126/ecfw_ptr.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <endian.h> +#include "ecfw_ptr.h" + +/* + * Address info for EC SMSC KBC1098/KBC1126 to find their firmware blobs, + * linked to CONFIG_ECFW_PTR_ADDR via src/arch/x86/bootblock.ld + */ +__attribute__((used, __section__(".ecfw_ptr"))) +const struct ecfw_ptr ecfw_ptr = { + .fw1.off = cpu_to_be16((uint16_t)(CONFIG_KBC1126_FW1_OFFSET >> 8)), + .fw1.inv = cpu_to_be16((uint16_t)~(CONFIG_KBC1126_FW1_OFFSET >> 8)), + .fw2.off = cpu_to_be16((uint16_t)(CONFIG_KBC1126_FW2_OFFSET >> 8)), + .fw2.inv = cpu_to_be16((uint16_t)~(CONFIG_KBC1126_FW2_OFFSET >> 8)), +}; diff --git a/src/ec/hp/kbc1126/ecfw_ptr.h b/src/ec/hp/kbc1126/ecfw_ptr.h new file mode 100644 index 0000000..acf54f2 --- /dev/null +++ b/src/ec/hp/kbc1126/ecfw_ptr.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EC_HP_KBC1126_PTR_H +#define _EC_HP_KBC1126_PTR_H + +#include <stdint.h> + +struct __attribute__((__packed__)) ecfw_addr { + /* 8-byte offset of firmware blob in big endian */ + uint16_t off; + /* bitwise inverse of "off", for error checking */ + uint16_t inv; +}; + +struct __attribute__((__packed__)) ecfw_ptr { + struct ecfw_addr fw1; + struct ecfw_addr fw2; +}; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/51671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Gerrit-Change-Number: 51671 Gerrit-PatchSet: 38 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/gpio: add variant_gpio_lock_config()
by Nick Vaccaro (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60274 to look at the new patch set (#2). Change subject: soc/intel/common/block/gpio: add variant_gpio_lock_config() ...................................................................... soc/intel/common/block/gpio: add variant_gpio_lock_config() Add variant_gpio_lock_config() to give variants a way to provide a list of gpios that the variant wants locked, such as gpios connected to the TPM. BUG=b:208827718 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0 to kernel. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e --- M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60274/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3edc309335b2751a85b479250ee0c470ea842c2e Gerrit-Change-Number: 60274 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add timestamp for cse_fw_sync
by Sridhar Siricilla (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60135 ) Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60135/comment/e6d42183_30b0bfb3 PS1, Line 14: (77,973) > 77 ms is quite long. […] This is expected on my board (which is based on ES silicon). I have measured cse_fw_sync() call during warm reboot time on QS Silicon, I see it only takes 2.3ms. 948:starting CSE firmware sync 589,639 (338) 949:finished CSE firmware sync 591,982 (2,343) -- To view, visit https://review.coreboot.org/c/coreboot/+/60135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Gerrit-Change-Number: 60135 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 17:25:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarein: Add power control for Sarien touchscreen
by EricR Lai (Code Review) 21 Dec '21

21 Dec '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32330 Change subject: mb/google/sarein: Add power control for Sarien touchscreen ...................................................................... mb/google/sarein: Add power control for Sarien touchscreen This change will save touchscreen power leakage 2-3mW in S0iX and increase T2 display time delay to meet display panel requirement. BUG=b:129899315 TEST= Measure touchscreen power from Sarien during S0iX Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0 --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32330/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e4a92a9..bdd134a 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -311,10 +311,12 @@ register "generic.desc" = ""Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" - register "generic.enable_off_delay_ms" = "100" + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x0" device i2c 10 on end @@ -324,10 +326,12 @@ register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" - register "generic.enable_off_delay_ms" = "100" + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end @@ -337,8 +341,10 @@ register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "enable_delay_ms" = "5" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" register "has_power_resource" = "1" device i2c 34 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/32330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0 Gerrit-Change-Number: 32330 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: docker/Makefile: Use all instead of all_without_gdb
by Hsuan-ting Chen (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Hsuan Ting Chen, Martin Roth, Paul Menzel. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60268 ) Change subject: docker/Makefile: Use all instead of all_without_gdb ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60268/comment/2bb490d6_01b9e87d PS1, Line 10: it > What fails? Add more contexts -- To view, visit https://review.coreboot.org/c/coreboot/+/60268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06c6d8e36dfd4e6a00ddec8b640b608ab1ba614c Gerrit-Change-Number: 60268 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 16:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: docker/Makefile: Use all instead of all_without_gdb
by Hsuan-ting Chen (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Hsuan Ting Chen, Martin Roth, Hsuan-ting Chen. Hello build bot (Jenkins), Hsuan Ting Chen, Martin Roth, HAOUAS Elyes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60268 to look at the new patch set (#2). Change subject: docker/Makefile: Use all instead of all_without_gdb ...................................................................... docker/Makefile: Use all instead of all_without_gdb After removing GDB from crossgcc in commit f32eed16 (buildgcc: Remove GDB from crossgcc), there is no target named all_without_gdb anymore and we should always build crossgcc with target all. But in util/docker/Makefile, we still try to build crossgcc with target all_without_gdb as default and will cause a build failure. Set CROSSGCC_PARAM from all_without_gdb to all to fix this issue. Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Change-Id: I06c6d8e36dfd4e6a00ddec8b640b608ab1ba614c --- M util/docker/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60268/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06c6d8e36dfd4e6a00ddec8b640b608ab1ba614c Gerrit-Change-Number: 60268 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021