coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screen
by Edward Doan (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: shkim, Henry Sun, Karthik Ramasubramanian. Edward Doan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60273 ) Change subject: mb/google/dedede/var/bugzzy: Increase reset_delay_ms for touch screen ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34cbc82e2d691266389d498e77d8389cdee23efe Gerrit-Change-Number: 60273 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 21 Dec 2021 16:15:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Add stylus function
by Aseda Aboagye (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Evan Green, Ren Kuo, Paul Menzel, Tyler Wang, Karthik Ramasubramanian. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60185 ) Change subject: mb/google/dedede/var/magolor: Add stylus function ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03 Gerrit-Change-Number: 60185 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 21 Dec 2021 15:31:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: FSP 2511 headers include.
by Tim Wawrzynczak (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Saurabh Mishra, Balaji Manigandan, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60259 ) Change subject: FSP 2511 headers include. ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: This FSP version has not landed in the chrome tree yet and the headers are not upstream (here) yet, so this does not compile right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/60259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c576f3 Gerrit-Change-Number: 60259 Gerrit-PatchSet: 3 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 15:03:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Enable I2C4
by Sean Rhodes (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Paul Menzel. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60264 ) Change subject: mb/starlabs/labtop: Enable I2C4 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60264/comment/e399299b_fc66454b PS2, Line 7: mb/starlabs/labtop: Enable I2C4 > Mayeb: […] It works fine without this -- To view, visit https://review.coreboot.org/c/coreboot/+/60264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd Gerrit-Change-Number: 60264 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 15:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Update Verb Table
by Sean Rhodes (Code Review) 21 Dec '21

21 Dec '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60282 ) Change subject: mb/starlabs/labtop: Update Verb Table ...................................................................... mb/starlabs/labtop: Update Verb Table Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1717f3916fa4d51cd34baa8a51b859389e06056f --- M src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c 1 file changed, 79 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/60282/1 diff --git a/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c index 7903d96..a37d72f 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c @@ -89,28 +89,38 @@ * Equalizer: * * AGC - * Threshold: - 6.00 dB - * Front Boost: + 6.00 dB - * Post Boost: + 6.00 dB + * Threshold: + 0.00 dB + * Front Boost: + 0.00 dB + * Post Boost: + 0.00 dB * * Low Pass Filter - * Boost Gain: Enabled - * BW: 200Hz - * Gain: + 4.00 dB + * Boost Gain: 1st Order Butterworth + * BW: 19000Hz + * Gain: + 0.00 dB * * Band Pass Filter 1 - * Fc: 240Hz - * BW: 400Hz - * Gain: - 4.00 dB + * Fc: 400Hz + * BW: 1000Hz + * Gain: - 2.00 dB * * Band Pass Filter 2 - * Fc: 16000Hz + * Fc: 550Hz * BW: 1000Hz - * Gain: + 12.00 dB + * Gain: - 4.50 dB + * + * Band Pass Filter 3 + * Fc: 6000Hz + * BW: 10000Hz + * Gain: - 3.00 dB + * + * Band Pass Filter 4 + * Fc: 18000Hz + * BW: 1000Hz + * Gain: - 0.50 dB * * High Pass Filter * Boost Gain: Enabled - * BW: 200Hz + * BW: 120Hz * Gain: - 4.00 dB * * Class D Amp @@ -118,92 +128,117 @@ * Resistance: 4ohms * * EQ Output - * Left: + 0.00 dB - * Right: + 0.00 dB + * Left: + 10.50 dB + * Right: + 10.50 dB * * VARQ * Q: 0.707 */ 0x05350000, - 0x053404DA, + 0x053417DA, 0x0535001d, 0x05340800, 0x0535001e, - 0x05340800, + 0x05341ACC, 0x05350003, - 0x05341F7A, + 0x05341FAF, 0x05350004, 0x0534FA18, 0x0535000F, - 0x0534C295, + 0x0534C4F6, 0x05350010, - 0x05341D73, + 0x05341B1F, 0x05350011, - 0x0534FA18, + 0x0534FCB6, 0x05350012, - 0x05341E08, + 0x0534C67E, 0x05350013, - 0x05341C10, + 0x053419A8, 0x05350014, - 0x05342FB2, + 0x0534F988, + 0x05350015, + 0x0534EA49, + + 0x05350016, + 0x0534FEB6, + 0x05350017, + 0x0534FB54, + + 0x05350018, + 0x05342A51, + 0x05350019, + 0x05341BD8, + + 0x0535001A, + 0x0534FF1B, 0x0535001B, - 0x05341F2C, + 0x0534F038, 0x0535001C, - 0x0534095C, + 0x05340000, 0x05450000, - 0x05440000, + 0x05441000, 0x0545001d, 0x05440800, 0x0545001e, - 0x05440800, + 0x05441ACC, 0x05450003, - 0x05441F7A, + 0x05441FAF, 0x05450004, 0x0544FA18, 0x0545000F, - 0x0544C295, + 0x0544C4F6, 0x05450010, - 0x05441D73, + 0x05441B1F, 0x05450011, - 0x0544FA18, + 0x0544FCB6, 0x05450012, - 0x05441E08, + 0x0544C67E, 0x05450013, - 0x05441C10, + 0x054419A8, 0x05450014, - 0x05442FB2, + 0x0544F988, + + 0x05450015, + 0x0544EA49, + 0x05450016, + 0x0544FEB6, + + 0x05450017, + 0x0544FB54, + 0x05450018, + 0x05442A51, + + 0x05450019, + 0x05441BD8, + 0x0545001A, + 0x0544FF1B, 0x0545001B, - 0x05441F2C, + 0x0544F038, 0x0545001C, - 0x0544095C, + 0x05440000, 0x05350000, - 0x0534C4DA, + 0x0534D7DA, 0x02050038, 0x02044901, 0x02050013, - 0x0204422F, + 0x0204292F, 0x02050016, - 0x02044E50, - - 0x02050012, - 0x0204EBC4, - 0x02050020, - 0x020451FF, + 0x02044C50, }; const u32 pc_beep_verbs[] = {}; -- To view, visit https://review.coreboot.org/c/coreboot/+/60282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1717f3916fa4d51cd34baa8a51b859389e06056f Gerrit-Change-Number: 60282 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Add PSE TSN support
by Werner Zeh (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56633 ) Change subject: soc/intel/elkhartlake: Add PSE TSN support ...................................................................... Patch Set 26: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56633/comment/8b27f561_79cecf68 PS26, Line 94: if (xtal_freq_enum != (XTAL_24_MHZ || XTAL_38_4_MHZ)) { This is wrong here (XTAL_24_MHZ || XTAL_38_4_MHZ is always true). It shouold be: if ((xtal_freq_enum != XTAL_24_MHZ) && (xtal_freq_enum != XTAL_38_4_MHZ)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Gerrit-Change-Number: 56633 Gerrit-PatchSet: 26 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 14:50:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/apcb: Add apcb_v3_edit tool
by Rob Barnes (Code Review) 21 Dec '21

21 Dec '21

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60281 ) Change subject: util/apcb: Add apcb_v3_edit tool ...................................................................... util/apcb: Add apcb_v3_edit tool apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject up to 16 SPDs into an existing APCB. The APCB must have a magic number at the top of each SPD slot. BUG=b:209486191 BRANCH=None TEST=Inject 4 SPDs into magic APCB, boot guybrush with modified APCB Change-Id: I9148977c415df41210a3a13a1cd9b3bc1504a480 --- A util/apcb/apcb_v3_edit.py M util/apcb/description.md 2 files changed, 157 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/60281/1 diff --git a/util/apcb/apcb_v3_edit.py b/util/apcb/apcb_v3_edit.py new file mode 100755 index 0000000..c243a9b --- /dev/null +++ b/util/apcb/apcb_v3_edit.py @@ -0,0 +1,154 @@ +#!/usr/bin/env python3 + +# Script for editing APCB_V3 binaries, such as injecting SPDs. + +import sys +import re +import argparse +from collections import namedtuple +from struct import * +import binascii +import os + +SPD_MAGIC = bytes.fromhex('f005ba110000') +EMPTY_SPD = b'\x00' * 512 + +spd_ssp_struct_fmt = '??B?IIBBBxIIBBBx' +spd_ssp_struct = namedtuple( + 'spd_ssp_struct', 'SpdValid, DimmPresent, \ + PageAddress, NvDimmPresent, \ + DramManufacturersIDCode, Address, \ + SpdMuxPresent, MuxI2CAddress, MuxChannel, \ + Technology, Package, SocketNumber, \ + ChannelNumber, DimmNumber') + +apcb_v3_header_fmt = 'HHHHBBBBBBH' +apcb_v3_header = namedtuple( + 'apcb_v3_header', 'GroupId, TypeId, SizeOfType, \ + InstanceId, ContextType, ContextFormat, UnitSize, \ + PriorityMask, KeySize, KeyPos, BoardMask') + +def parseargs(): + parser = argparse.ArgumentParser(description='Inject SPDs and SPD GPIO \ + selection pins into APCB binaries') + parser.add_argument( + 'apcb_in', + type=str, + help='APCB input file') + parser.add_argument( + 'apcb_out', + type=str, + help='APCB output file') + parser.add_argument( + '--spd_sources', + nargs='+', + help='List of SPD sources') + parser.add_argument( + '--hex', + action='store_true', + help='SPD input file is hex encoded, binary otherwise') + parser.add_argument( + '--strip_manufacturer_information', + action='store_true', + help='Strip all manufacturer information from SPD') + return parser.parse_args() + + +def chksum(data): + sum = 0 + for b in data[:16] + data[17:]: + sum = (sum + b) & 0xff + return (0x100 - sum) & 0xff + + +def inject(orig, insert, offset): + return b''.join([orig[:offset], insert, orig[offset + len(insert):]]) + + +def main(): + args = parseargs() + + print("Reading input APCB from %s" % (args.apcb_in)) + + apcb = open(args.apcb_in, 'rb').read() + + orig_apcb_len = len(apcb) + + assert chksum(apcb) == apcb[16], "Checksum is invalid" + + spds = [] + for spd_source in args.spd_sources: + spd_data = bytes.fromhex(re.sub(r'\s+', '', open(spd_source, 'rb').read().decode().strip())) + assert(len(spd_data) == 512) + spds.append(spd_data) + + spd_offset = 0 + instance = 0 + while True: + spd_offset = apcb.find(SPD_MAGIC, spd_offset) + if spd_offset < 0: + print('No more SPD magic numbers found in APCB') + break + + spd_ssp_offset = spd_offset - calcsize(spd_ssp_struct_fmt) + spd_ssp_bytes = apcb[spd_ssp_offset:spd_offset] + spd_ssp = spd_ssp_struct._make( + unpack(spd_ssp_struct_fmt, spd_ssp_bytes)) + + assert spd_ssp.DimmNumber >= 0 and spd_ssp.DimmNumber <= 1, \ + "Unexpected dimm number found in APCB" + assert spd_ssp.ChannelNumber >= 0 and spd_ssp.ChannelNumber <= 1, \ + "Unexpected channel number found in APCB" + + print("Found SPD instance %d with channel %d and dimm %d " + "at offset 0x%x" % (instance, spd_ssp.ChannelNumber, + spd_ssp.DimmNumber, spd_offset)) + + # APCB V3 header is above first channel 0 entry + if spd_ssp.ChannelNumber == 0: + apcb_v3_header_offset = spd_ssp_offset - \ + calcsize(apcb_v3_header_fmt) - 4 + apcb_v3_header_bytes = apcb[apcb_v3_header_offset: + apcb_v3_header_offset + calcsize(apcb_v3_header_fmt)] + apcb_v3 = apcb_v3_header._make( + unpack(apcb_v3_header_fmt, apcb_v3_header_bytes)) + apcb_v3 = apcb_v3._replace(BoardMask=(1 << instance)) + + if instance < len(spds): + print("SpdValid %d, DimmPresent %d" % + (spd_ssp.SpdValid, spd_ssp.DimmPresent)) + print("Enabling channel %d, dimm %d and injecting SPD" % + (spd_ssp.ChannelNumber, spd_ssp.DimmNumber)) + spd_ssp = spd_ssp._replace(SpdValid=True, DimmPresent=True) + spd = spds[instance] + else: + print("Disabling channel %d, dimm %d and clearing SPD" % + (spd_ssp.ChannelNumber, spd_ssp.DimmNumber)) + spd_ssp = spd_ssp._replace(SpdValid=False, DimmPresent=False) + spd = EMPTY_SPD + + assert len(spd) == 512, "Expected SPD to be 512 bytes, got %d" % len(spd) + + apcb = inject(apcb, pack(spd_ssp_struct_fmt, *spd_ssp), spd_ssp_offset) + apcb = inject(apcb, spd, spd_offset) + if spd_ssp.ChannelNumber == 0: + apcb = inject(apcb, pack(apcb_v3_header_fmt, *apcb_v3), apcb_v3_header_offset) + else: + instance += 1 + + spd_offset += 512 + + print("Fixing checksum and writing to %s" % (args.apcb_out)) + + apcb = inject(apcb, bytes([chksum(apcb)]), 16) + + assert chksum(apcb) == apcb[16], "Checksum is invalid" + assert orig_apcb_len == len(apcb), \ + "The size of the APCB binary changed, this should not happen." + + print(f'Writing {len(apcb)} bytes to {args.apcb_out}') + + open(args.apcb_out, 'wb').write(apcb) + +if __name__ == "__main__": + main() diff --git a/util/apcb/description.md b/util/apcb/description.md index 674243a..827d55b 100644 --- a/util/apcb/description.md +++ b/util/apcb/description.md @@ -2,3 +2,6 @@ * _apcb_edit.py_ - This tool allows patching an existing APCB binary with specific SPDs and GPIO selection pins. `Python3` + +* _apcb_v3_edit.py_ - This tool allows patching an existing APCB_v3 binary with + up to 16 specific SPDs. `Python3` -- To view, visit https://review.coreboot.org/c/coreboot/+/60281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9148977c415df41210a3a13a1cd9b3bc1504a480 Gerrit-Change-Number: 60281 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] smp/spinlock: Use compiler builtins
by Kyösti Mälkki (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Raul Rangel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60253 ) Change subject: [RFC] smp/spinlock: Use compiler builtins ...................................................................... Patch Set 2: (1 comment) File src/include/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/60253/comment/2b505c15_50b57597 PS1, Line 22: return !__atomic_load_1(&lock->locked, __ATOMIC_RELAXED); > Inverted Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6694784aa0810cd877886ef95434f62e3aefce6c Gerrit-Change-Number: 60253 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 14:04:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] smp/spinlock: Use compiler builtins
by build bot (Jenkins) (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Raul Rangel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60253 ) Change subject: [RFC] smp/spinlock: Use compiler builtins ...................................................................... Patch Set 2: (2 comments) File src/include/smp/spinlock.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135973): https://review.coreboot.org/c/coreboot/+/60253/comment/7a3aff86_1587c43f PS2, Line 11: #define DECLARE_SPIN_LOCK(x) static struct spinlock x; macros should not use a trailing semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135973): https://review.coreboot.org/c/coreboot/+/60253/comment/05fbc824_7b976802 PS2, Line 27: while (!spinlock_try_lock(lock)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/60253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6694784aa0810cd877886ef95434f62e3aefce6c Gerrit-Change-Number: 60253 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 21 Dec 2021 14:03:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] src/console: Replace to mutex as printk serialization
by Kyösti Mälkki (Code Review) 21 Dec '21

21 Dec '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60280 ) Change subject: [WIP] src/console: Replace to mutex as printk serialization ...................................................................... [WIP] src/console: Replace to mutex as printk serialization If COOP_MULTITASKING is enabled, printk() may call switch threads while console_lock is held. To avoid a deadlock, when failing to acquire console_lock, let other threads execute. Ultimately some of the other threads will call thread_yield() without holding console_lock and let another thread continue here. Change-Id: Id5a48afe40ca86e55e91a00b8a4ee31da09fb9cb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/printk.c A src/include/mutex.h 2 files changed, 37 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/60280/1 diff --git a/src/console/printk.c b/src/console/printk.c index 1ed39cb..b54cd9a 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <console/streams.h> #include <console/vtxprintf.h> +#include <mutex.h> #include <smp/spinlock.h> #include <smp/node.h> #include <timer.h> @@ -80,7 +81,7 @@ if (log_this < CONSOLE_LOG_FAST) return 0; - spin_lock(&console_lock); + mutex_lock(&console_lock); console_time_run(); @@ -93,7 +94,7 @@ console_time_stop(); - spin_unlock(&console_lock); + mutex_unlock(&console_lock); return i; } diff --git a/src/include/mutex.h b/src/include/mutex.h new file mode 100644 index 0000000..d4642f9 --- /dev/null +++ b/src/include/mutex.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MUTEX_H +#define _MUTEX_H + +#include <arch/cpu.h> +#include <smp/spinlock.h> +#include <thread.h> + +static inline void mutex_lock(struct spinlock *lock) +{ + while (!spinlock_try_lock(lock)) { + /* + * If we failed to get the lock, wait until it's been unlocked before trying to + * read-modify-write. This helps prevent excessive cache misses. + */ + while (spinlock_is_locked(lock)) { + /* + * Threads are only available on the BSP, so if this code is running + * on an AP, yielding will fail. In that case just sleep for a bit + * and try again. + */ + if (thread_yield() < 0) + cpu_relax(); + } + } +} + +static inline void mutex_unlock(struct spinlock *lock) +{ + spin_unlock(lock); +} + +#endif /* _MUTEX_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a48afe40ca86e55e91a00b8a4ee31da09fb9cb Gerrit-Change-Number: 60280 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021