coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting
by Kenneth Chan (Code Review) 24 Dec '21

24 Dec '21

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60328 ) Change subject: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting ...................................................................... mb/google/guybrush/var/dewatt: disable unused PCIe clock setting Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt. BUG=b:211566312 TEST=emerge-guybrush coreboot Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: If449453bc60ed41e104346429babc06a73acef64 --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/60328/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index fb4225b..8696d46 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -18,6 +18,10 @@ register "telemetry_vddcrsocfull_scale_current_mA" = "31481" #mA register "telemetry_vddcrsocoffset" = "193" + # general purpose PCIe clock output configuration + register "gpp_clk_config[1]" = "GPP_CLK_OFF" + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + # I2C Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/60328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If449453bc60ed41e104346429babc06a73acef64 Gerrit-Change-Number: 60328 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
by Cliff Huang (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Cliff Huang, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60183 ) Change subject: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Gerrit-Change-Number: 60183 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 24 Dec 2021 00:08:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function
by Cliff Huang (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Cliff Huang, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60179 ) Change subject: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Gerrit-Change-Number: 60179 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 24 Dec 2021 00:07:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/lindar: Probe for RT1011_ALC5682I_I2S
by Felix Singer (Code Review) 24 Dec '21

24 Dec '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60327 ) Change subject: mb/google/volteer/lindar: Probe for RT1011_ALC5682I_I2S ...................................................................... mb/google/volteer/lindar: Probe for RT1011_ALC5682I_I2S My variant of lindar uses RT1011_ALC5682I_I2S and currently it isn't probed, which causes the audio controller being disabled. Thus, probe for it. Change-Id: Ib848b65b4939dd43d78cb7fd7b8b271e95f324be Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/lindar/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/60327/1 diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 2eb482d..cb9ee7a 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -274,6 +274,7 @@ probe AUDIO MAX98373_ALC5682_SNDW probe AUDIO MAX98373_ALC5682I_I2S_UP4 probe AUDIO MAX98360_ALC5682I_I2S + probe AUDIO RT1011_ALC5682I_I2S end device ref pcie_rp9 on chip soc/intel/common/block/pcie/rtd3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib848b65b4939dd43d78cb7fd7b8b271e95f324be Gerrit-Change-Number: 60327 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for ...
by Angel Pons (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Ronak Kanabar, Zhuohao Lee, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60031 ) Change subject: Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"" ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2 Gerrit-Change-Number: 60031 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 22:20:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/haswell: Program Mini-HD EM4 and EM5 registers
by Angel Pons (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50143 ) Change subject: nb/intel/haswell: Program Mini-HD EM4 and EM5 registers ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/haswell/minihd.c: https://review.coreboot.org/c/coreboot/+/50143/comment/08f5a692_77b66fc6 PS3, Line 67: /* Mini-HD configuration */ : reg32 = read32(base + 0x100c); : reg32 &= 0xfffc0000; : reg32 |= 0x4; : write32(base + 0x100c, reg32); : : reg32 = read32(base + 0x1010); : reg32 &= 0xfffc0000; : reg32 |= 0x4b; : write32(base + 0x1010, reg32); Looks like this programs the EM4/EM5 registers with fixed values. Given that Broadwell code also has this, I'd prefer to look into removing this once the code is deduplicated. -- To view, visit https://review.coreboot.org/c/coreboot/+/50143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4542b7b66afc852e6bf288729c10ae2182585f Gerrit-Change-Number: 50143 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jamal Wright <Crabstorage(a)getbackinthe.kitchen> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 22:16:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/haswell/gma.c: Refactor CdClk init code
by Angel Pons (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Paul Menzel, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50136 ) Change subject: nb/intel/haswell/gma.c: Refactor CdClk init code ...................................................................... Patch Set 5: (1 comment) File src/northbridge/intel/haswell/gma.c: https://review.coreboot.org/c/coreboot/+/50136/comment/33e83433_1a2337d4 PS3, Line 369: * ULX defaults to 337MHz with possible override for 450MHz : * ULT is fixed at 450MHz : * others default to 540MHz with possible override for 450MHz > It's aligning the numbers. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa9e9085d5dca0ced7bed4ca8fece139c29bc46c Gerrit-Change-Number: 50136 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jamal Wright <Crabstorage(a)getbackinthe.kitchen> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 22:12:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Felix Held (Code Review) 24 Dec '21

24 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60131 ) Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... mb/google/hatch/var/scout: improve USB2 port 4 strength Set USB2 port 4 pre emphasis to 15mV for passing USB2 port 4 SI (margin eye diagram). BUG=b:210755120 TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60131 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/hatch/variants/scout/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index 9b33621..07c64db 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -42,7 +42,14 @@ .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port register "usb2_ports[4]" = "{ .enable = 1, .ocpin = OC_SKIP, -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 8 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb: Remove dot from end of non-sentence comment
by Felix Held (Code Review) 24 Dec '21

24 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60248 ) Change subject: mb: Remove dot from end of non-sentence comment ...................................................................... mb: Remove dot from end of non-sentence comment Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/glados/variants/asuka/include/variant/gpio.h M src/mainboard/google/glados/variants/caroline/include/variant/gpio.h M src/mainboard/google/glados/variants/cave/include/variant/gpio.h M src/mainboard/google/glados/variants/chell/include/variant/gpio.h M src/mainboard/google/glados/variants/glados/include/variant/gpio.h M src/mainboard/google/glados/variants/lars/include/variant/gpio.h M src/mainboard/google/glados/variants/sentry/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h M src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h M src/mainboard/intel/kunimitsu/gpio.h M src/mainboard/intel/saddlebrook/gpio.h M src/mainboard/prodrive/hermes/gpio.c M src/mainboard/starlabs/labtop/variants/tgl/gpio.c M src/mainboard/system76/lemp9/gpio.h 16 files changed, 16 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index 3ee5532..758b7cc 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -214,7 +214,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 7f8787c..fe31102 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -231,7 +231,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index 0eb7de7..e96a78a 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -223,7 +223,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index e152862..3260472 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -217,7 +217,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 248e7dd..b812fb7 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -220,7 +220,7 @@ /* LANPHYC */ /* GPD11 */ }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index ee55512..7cf56aa 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -208,7 +208,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 06f6cd8..10291b0 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -216,7 +216,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index aaec3eb..fb47e6f 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -257,7 +257,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h index 26eb1d9..11a6b82 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -193,7 +193,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index d2e76d9..9c252e2 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -193,7 +193,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index 44997c7..1c112df 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -159,7 +159,7 @@ }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index a436d8f..c4628f2 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -217,7 +217,7 @@ /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index b012462..da9c27e 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -245,7 +245,7 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/prodrive/hermes/gpio.c b/src/mainboard/prodrive/hermes/gpio.c index f228ef8..5cb901d 100644 --- a/src/mainboard/prodrive/hermes/gpio.c +++ b/src/mainboard/prodrive/hermes/gpio.c @@ -369,7 +369,7 @@ }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { /* Get PCIe out of reset */ PAD_CFG_GPO(GPP_K0, 1, DEEP), /* PERST_PCH_SLOTS_n */ diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c index 81f6cb7..a0fc12c 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -7,7 +7,7 @@ * using the stock BIOS and with coreboot. */ -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/lemp9/gpio.h index 60cc7b6..518a500 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/lemp9/gpio.h @@ -10,7 +10,7 @@ /* Name format: <pad name> / <net/pin name in schematics> */ -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Gerrit-Change-Number: 60248 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb: Add space before closing comment block keyword
by Felix Held (Code Review) 24 Dec '21

24 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60247 ) Change subject: mb: Add space before closing comment block keyword ...................................................................... mb: Add space before closing comment block keyword Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/blipper/gpio.c M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/bugzzy/gpio.c M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/galtic/gpio.c M src/mainboard/google/dedede/variants/gooey/gpio.c M src/mainboard/google/dedede/variants/haboki/gpio.c M src/mainboard/google/dedede/variants/kracko/gpio.c M src/mainboard/google/dedede/variants/metaknight/gpio.c M src/mainboard/google/dedede/variants/pirika/gpio.c M src/mainboard/google/dedede/variants/sasuke/gpio.c M src/mainboard/google/dedede/variants/sasukette/gpio.c M src/mainboard/google/dedede/variants/storo/gpio.c M src/mainboard/google/dedede/variants/waddledee/gpio.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c 24 files changed, 25 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 3bee320..e1b920a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ /* A0 : ESPI_IO0 */ diff --git a/src/mainboard/google/dedede/variants/blipper/gpio.c b/src/mainboard/google/dedede/variants/blipper/gpio.c index 6af1ed7..8b754ee 100644 --- a/src/mainboard/google/dedede/variants/blipper/gpio.c +++ b/src/mainboard/google/dedede/variants/blipper/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index 123a3bb..5085917 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c index a218c5e..16cf61b 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c +++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c @@ -5,7 +5,7 @@ #include <bootstate.h> #include <fw_config.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index 97865474..fa4d4d5 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -7,14 +7,14 @@ #include <fw_config.h> #include <ec/google/chromeec/ec.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config not_board6or8_gpio_table[] = { /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), }; -/* bid6: Pad configuration for board version 6 or 8 in ramstage*/ +/* bid6: Pad configuration for board version 6 or 8 in ramstage */ static const struct pad_config board6or8_gpio_table[] = { /* A10 : WWAN_EN */ diff --git a/src/mainboard/google/dedede/variants/galtic/gpio.c b/src/mainboard/google/dedede/variants/galtic/gpio.c index 79646b5..e2e6669 100644 --- a/src/mainboard/google/dedede/variants/galtic/gpio.c +++ b/src/mainboard/google/dedede/variants/galtic/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A11 : TOUCH_RPT_EN */ diff --git a/src/mainboard/google/dedede/variants/gooey/gpio.c b/src/mainboard/google/dedede/variants/gooey/gpio.c index 123a3bb..5085917 100644 --- a/src/mainboard/google/dedede/variants/gooey/gpio.c +++ b/src/mainboard/google/dedede/variants/gooey/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/haboki/gpio.c b/src/mainboard/google/dedede/variants/haboki/gpio.c index 03b9a45..12286c6 100644 --- a/src/mainboard/google/dedede/variants/haboki/gpio.c +++ b/src/mainboard/google/dedede/variants/haboki/gpio.c @@ -6,7 +6,7 @@ #include <fw_config.h> #include <ec/google/chromeec/ec.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), diff --git a/src/mainboard/google/dedede/variants/kracko/gpio.c b/src/mainboard/google/dedede/variants/kracko/gpio.c index b4c00bd..e8422fd 100644 --- a/src/mainboard/google/dedede/variants/kracko/gpio.c +++ b/src/mainboard/google/dedede/variants/kracko/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/metaknight/gpio.c b/src/mainboard/google/dedede/variants/metaknight/gpio.c index af37d24..072ea7b 100644 --- a/src/mainboard/google/dedede/variants/metaknight/gpio.c +++ b/src/mainboard/google/dedede/variants/metaknight/gpio.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/pirika/gpio.c b/src/mainboard/google/dedede/variants/pirika/gpio.c index 79646b5..e2e6669 100644 --- a/src/mainboard/google/dedede/variants/pirika/gpio.c +++ b/src/mainboard/google/dedede/variants/pirika/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A11 : TOUCH_RPT_EN */ diff --git a/src/mainboard/google/dedede/variants/sasuke/gpio.c b/src/mainboard/google/dedede/variants/sasuke/gpio.c index f101215..8aa9f29 100644 --- a/src/mainboard/google/dedede/variants/sasuke/gpio.c +++ b/src/mainboard/google/dedede/variants/sasuke/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/sasukette/gpio.c b/src/mainboard/google/dedede/variants/sasukette/gpio.c index d9b1307..78d72c7 100644 --- a/src/mainboard/google/dedede/variants/sasukette/gpio.c +++ b/src/mainboard/google/dedede/variants/sasukette/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/storo/gpio.c b/src/mainboard/google/dedede/variants/storo/gpio.c index a73caf5..73b3c2a 100644 --- a/src/mainboard/google/dedede/variants/storo/gpio.c +++ b/src/mainboard/google/dedede/variants/storo/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/waddledee/gpio.c b/src/mainboard/google/dedede/variants/waddledee/gpio.c index 0905e8f..dbb12dc 100644 --- a/src/mainboard/google/dedede/variants/waddledee/gpio.c +++ b/src/mainboard/google/dedede/variants/waddledee/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* E5 : AP_SUB_IO_2 */ PAD_CFG_GPO(GPP_E5, 0, PLTRST), diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index c9b533e..4cdc427 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -8,7 +8,7 @@ #include <gpio.h> #include <soc/gpio.h> -/* GPIO configuration in ramstage*/ +/* GPIO configuration in ramstage */ /* Please make sure that *ALL* GPIOs are configured in this table */ static const struct soc_amd_gpio base_gpio_table[] = { /* PWR_BTN_L */ diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 8a04bd9..d553180 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* SSD1_PWREN CPU SSD1 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST), diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c index 9d17c80..b2e2eec 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /*BT_RF_KILL_N*/ PAD_CFG_GPO(GPP_E11, 1, DEEP), diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index df06865..94a6a79 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST), diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index df06865..94a6a79 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST), diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 82b3931..27395db 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* WWAN_WAKE_N */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index f067af7..b9fdac8 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ PAD_CFG_GPO(GPP_B16, 1, DEEP), diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 889d4e6..1c007d7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -5,7 +5,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ PAD_CFG_GPO(GPP_B16, 1, DEEP), diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c index 91c0417..b6c755a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* Community 0 - GpioGroup GPP_B */ PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Gerrit-Change-Number: 60247 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021