coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: soc/medaitek/mt8195: adjust USB phy shift value
by Rex-BC Chen (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Hung-Te Lin, Tianping Fang, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60312 ) Change subject: soc/medaitek/mt8195: adjust USB phy shift value ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: @yu-ping, could you help to review this patch? Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/60312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Gerrit-Change-Number: 60312 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Tianping Fang <tianping.fang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 24 Dec 2021 07:46:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for ...
by Ronak Kanabar (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, Patrick Rudolph. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60031 ) Change subject: Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2 Gerrit-Change-Number: 60031 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 24 Dec 2021 06:46:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST
by Subrata Banik (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60320 ) Change subject: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Meera, we would like to fix all the lock pins at time, b/c Finger printer can't work after reboot as […] Agree with Eric and this has to be done for all variant. Let me create a bug and assign to me to come up with a new macro as discussed over buganizer -- To view, visit https://review.coreboot.org/c/coreboot/+/60320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee Gerrit-Change-Number: 60320 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 24 Dec 2021 06:09:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid
by Subrata Banik (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Reka Norman, Paul Menzel, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60271 ) Change subject: mb/google/brya: Add new baseboard nissa with variants nivviks and nereid ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60271/comment/7cb700d1_ae9514c7 PS4, Line 10: Also nit: Also, File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/60271/comment/f9970cce_536f7c65 PS4, Line 3: select SOC_INTEL_ALDERLAKE_PCH_P can this one and line #10 can move to a separate CL to make it clear. Like its been done here for ADLRVP? https://review.coreboot.org/c/coreboot/+/59804/6/src/mainboard/intel/adlrvp… -- To view, visit https://review.coreboot.org/c/coreboot/+/60271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5 Gerrit-Change-Number: 60271 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 24 Dec 2021 06:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/taniks:Correct usb{23}_port_number fields
by Joey Peng (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: YH Lin, Tim Wawrzynczak. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60333 ) Change subject: mb/google/brya/var/taniks:Correct usb{23}_port_number fields ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/60333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcf107df90dc598fd31485fa0299e890ee7a9ccd Gerrit-Change-Number: 60333 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 24 Dec 2021 06:00:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Subrata Banik (Code Review) 24 Dec '21

24 Dec '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59937 ) Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... mb/intel/adlrvp: Configure GPIOs for Alder Lake-N List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/early_gpio_n.c A src/mainboard/intel/adlrvp/gpio_n.c 3 files changed, 250 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 04c1645..0b658e5 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -7,6 +7,9 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_M),y) bootblock-y += early_gpio_m.c ramstage-y += gpio_m.c +else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) +bootblock-y += early_gpio_n.c +ramstage-y += gpio_n.c else bootblock-y += early_gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/early_gpio_n.c b/src/mainboard/intel/adlrvp/early_gpio_n.c new file mode 100644 index 0000000..3eb1cea --- /dev/null +++ b/src/mainboard/intel/adlrvp/early_gpio_n.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), +}; + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/adlrvp/gpio_n.c b/src/mainboard/intel/adlrvp/gpio_n.c new file mode 100644 index 0000000..8e395e5 --- /dev/null +++ b/src/mainboard/intel/adlrvp/gpio_n.c @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ESPI_IO0_EC_R / ESPI_IO0_HDR */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + /* ESPI_IO1_EC_R / ESPI_IO1_HDR */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + /* ESPI_IO2_EC_R / ESPI_IO2_HDR */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + /* ESPI_IO3_EC_R / ESPI_IO3_HDR */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + /* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + /* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + /* ESPI_CLK_EC_R / ESPI_CLK_HDR */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + + /* GPPC_E7_EC_SMI_N */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* CLKREQ0_M2_SSD_N */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* M2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* M2_SSD_RST_N */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* M2_SSD_DEVSLP */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), + + /* TYPEA_CONN23_USB2_P8_OC1_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* CRD1_PWREN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* TCP1_DISP_AUX_P_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), + /* TCP1_DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), + /* TCP0_DISP_AUX_P_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E22, 0, PLTRST), + /* TCP0_DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + + /* EDP1_HPD_MIPI_PNL_RST */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* X1_SLOT_PWREN */ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), + /* SML0_CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* SML0_DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* CLKREQ3_X1PCIE_SLOT_N */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* X1_PCIE_SLOT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT), + /* X1_Slot_RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* CLKREQ1_WWAN_N */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPPC_D15_M.2_WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_PWREN */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* WWAN WAKE N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI + /* SRCCLK_OEB6 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3), + /* GPPC_F6_CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 1, PLTRST), + /* WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_F15, 1, PLTRST), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* PM_SLP_DRAM_N */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + /* CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* CODEC_INT_N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* SNDW0_CLK_HDR */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW0_DATA_HDR */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW1_CLK_DMIC_CLK_A_0 */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* SNDW1_DATA_DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* SNDW2_CLK_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* SNDW2_DATA_R */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* SOC_DMIC0_SNDW3_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* SOC_DMIC0_SNDW3_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* DDIB_DP_HDMI_ALS_HDP */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* 8 : M.2_BTWIFI_SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* 9 : GPD_9_SLP_WLAN_N */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + + /* GPIO pin for PCIE SRCCLKREQB_2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* H2 : WLAN_RST_N */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* CAM_PRIVACY_LED */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* B16 : I2C5 SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5 SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* D13 : WIFI_WAKE_N */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + + /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2 : CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4 : CNV_RF_RESET_R_N */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ_R */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 13 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/kano: Set vGPIO reset type
by David Wu (Code Review) 24 Dec '21

24 Dec '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60334 ) Change subject: mb/google/brya/var/kano: Set vGPIO reset type ...................................................................... mb/google/brya/var/kano: Set vGPIO reset type Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207527331 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b --- M src/mainboard/google/brya/variants/kano/gpio.c 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/60334/1 diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index d77abea..e8c9032 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -139,26 +139,26 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* CPU PCIe VGPIO for PEG60 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; static const struct pad_config romstage_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b Gerrit-Change-Number: 60334 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: util/futility: Ensure futility checks for flashrom as a dep
by Yu-Ping Wu (Code Review) 24 Dec '21

24 Dec '21

Attention is currently required from: Hung-Te Lin, Martin Roth - Personal, Edward O'Callaghan, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60236 ) Change subject: util/futility: Ensure futility checks for flashrom as a dep ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9744424f75299eb8335c1c0c2aca2808bde829d Gerrit-Change-Number: 60236 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth - Personal <martinroth(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin Roth - Personal <martinroth(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 24 Dec 2021 03:51:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/taniks:Correct usb{23}_port_number fields
by Joey Peng (Code Review) 24 Dec '21

24 Dec '21

Joey Peng has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60333 ) Change subject: mb/google/brya/var/taniks:Correct usb{23}_port_number fields ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcf107df90dc598fd31485fa0299e890ee7a9ccd Gerrit-Change-Number: 60333 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: mb/google/brya/var/taniks:Correct usb{23}_port_number fields
by Joey Peng (Code Review) 24 Dec '21

24 Dec '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60333 ) Change subject: mb/google/brya/var/taniks:Correct usb{23}_port_number fields ...................................................................... mb/google/brya/var/taniks:Correct usb{23}_port_number fields Since commit d448f8ce has merged, we have to change the USB-2 and USB-3 ports to new naming for taniks overrietree. BUG=b:211923717 TEST=emerge-brya coreboot and build without errors. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ifcf107df90dc598fd31485fa0299e890ee7a9ccd --- M src/mainboard/google/brya/variants/taniks/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/60333/1 diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index deb31ce..cb8c99a 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -365,13 +365,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn1 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcf107df90dc598fd31485fa0299e890ee7a9ccd Gerrit-Change-Number: 60333 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021