coreboot-gerrit December 2021

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Change in coreboot[master]: mb/acer/g43t-am3: Add documentation
by Angel Pons (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Felix Singer, Paul Menzel, Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56838 ) Change subject: mb/acer/g43t-am3: Add documentation ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File Documentation/mainboard/acer/g43t-am3.md: https://review.coreboot.org/c/coreboot/+/56838/comment/342587f5_2d69e2cd PS2, Line 108: flashrom -p internal -r backup.rom > Using `--noverify-all` instead of bypassing the IFD restrictions sounds like a good habit. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e296b3efbff0260f32badc699f1062f9885fa53 Gerrit-Change-Number: 56838 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Comment-Date: Thu, 23 Dec 2021 21:50:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/reef: Drop unnecessary option
by Angel Pons (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60149 ) Change subject: mb/google/reef: Drop unnecessary option ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f2ffd1e7b9ad2fab500b83c4cc56c9fc2d161ab Gerrit-Change-Number: 60149 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Thu, 23 Dec 2021 21:50:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Refactor ACPI CNVS generation ...................................................................... ChromeOS: Refactor ACPI CNVS generation Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen_extern.asl M src/acpi/dsdt_top.asl M src/lib/hardwaremain.c M src/mainboard/amd/majolica/mainboard.c M src/mainboard/google/auron/mainboard.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/cyan/mainboard.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/deltaur/mainboard.c M src/mainboard/google/drallion/ramstage.c M src/mainboard/google/eve/mainboard.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/glados/mainboard.c M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/jecht/mainboard.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/poppy/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/zork/mainboard.c M src/mainboard/intel/adlrvp/mainboard.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/coffeelake_rvp/mainboard.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/glkrvp/mainboard.c M src/mainboard/intel/icelake_rvp/mainboard.c M src/mainboard/intel/jasperlake_rvp/mainboard.c M src/mainboard/intel/kblrvp/mainboard.c M src/mainboard/intel/kunimitsu/mainboard.c M src/mainboard/intel/shadowmountain/mainboard.c M src/mainboard/intel/strago/mainboard.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/samsung/lumpy/mainboard.c M src/mainboard/samsung/stumpy/mainboard.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/acpi/chromeos.asl M src/vendorcode/google/chromeos/acpi/gnvs.asl M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h 51 files changed, 15 insertions(+), 143 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl index c778376..74193e1 100644 --- a/src/acpi/acpigen_extern.asl +++ b/src/acpi/acpigen_extern.asl @@ -11,7 +11,3 @@ External (GNVS, OpRegionObj) External (DNVS, OpRegionObj) #endif - -#if CONFIG(CHROMEOS_NVS) -External (CNVS, OpRegionObj) -#endif diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index 7b9b2d8..b8be798 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -4,7 +4,6 @@ #if CONFIG(CHROMEOS_NVS) /* Chrome OS specific */ -#include <vendorcode/google/chromeos/acpi/gnvs.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 28c2b82..b646e0c 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -24,7 +24,7 @@ #include <timer.h> #include <timestamp.h> #include <types.h> -#include <vendorcode/google/chromeos/gnvs.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <version.h> static boot_state_t bs_pre_device(void *arg); diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index 2dd2d57..252763b 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -7,7 +7,6 @@ #include <soc/acpi.h> #include <string.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -95,8 +94,6 @@ init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 12d5a68..f465d07 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "variant.h" @@ -29,7 +28,6 @@ { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7eba3c2..b35e005 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -4,7 +4,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -25,7 +24,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 6287d2c..b07a151 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <ec/ec.h> #include <soc/ramstage.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <fw_config.h> static void add_fw_config_oem_string(const struct fw_config *config, void *arg) @@ -60,7 +59,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->get_smbios_strings = mainboard_smbios_strings; } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 6145dc7..87ce61f 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -14,7 +14,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <ec/quanta/ene_kb3940q/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -258,7 +257,6 @@ { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index b8266b3..1e0006c 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(struct device *dev) @@ -16,7 +15,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index dba4795..700b3e3 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -9,7 +9,6 @@ #include <security/tpm/tss.h> #include <soc/soc_chip.h> #include <vb2_api.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_update_soc_chip_config(void) { @@ -68,7 +67,6 @@ { dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index e1cdb96..9812d9f 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -4,14 +4,8 @@ #include <baseboard/variants.h> #include <device/device.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; @@ -26,5 +20,4 @@ struct chip_operations mainboard_ops = { .init = mainboard_chip_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index d44c7b1..7c34c0d 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -4,7 +4,6 @@ #include <smbios.h> #include <soc/ramstage.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, @@ -32,12 +31,6 @@ gpio_configure_pads(gpio_table, num_gpios); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 35c0a61..4abb91e 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/nhlt.h> #include "gpio.h" @@ -58,7 +57,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 307fadd..13bc9b7 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -17,7 +17,6 @@ #include <soc/nhlt.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -223,7 +222,6 @@ mainboard_set_power_limits(soc_conf); dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 0d6a499..faa80b9 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -7,7 +7,6 @@ #include <gpio.h> #include <soc/nhlt.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static const char *oem_id_maxim = "INTEL"; @@ -96,7 +95,6 @@ { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index c50304d..cab5706 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -10,7 +10,6 @@ #include <gpio.h> #include <soc/acpi.h> #include <variant/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #define BACKLIGHT_GPIO GPIO_129 #define WWAN_AUX_RST_GPIO GPIO_18 @@ -197,7 +196,6 @@ { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; init_tables(); diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 93864b2..86065f9 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_silicon_init_params(FSPS_UPD *supd) { @@ -36,7 +35,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; variant_mainboard_enable(dev); } diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index fd7e9e2..3c255b7 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" static void mainboard_init(struct device *dev) @@ -15,7 +14,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e54ac74..2cd88b8 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -17,7 +17,6 @@ #include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> -#include <vendorcode/google/chromeos/chromeos.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -147,7 +146,6 @@ /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } int mainboard_get_xhci_oc_map(uint16_t *map) diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index c4b621a..4c98761 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -16,7 +16,6 @@ #include <southbridge/intel/common/gpio.h> #include <smbios.h> #include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG(VGA_ROM_RUN) static int int15_handler(void) @@ -170,7 +169,6 @@ { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; #if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index fbebe57..a614763 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -20,7 +20,6 @@ #include <soc/nhlt.h> #include <soc/pci_devs.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> @@ -140,7 +139,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 16695db..eeb3ce4 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -10,7 +10,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <ec/compal/ene932/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -61,7 +60,6 @@ { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 0a3fe1f..0e6c7b9 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -6,7 +6,6 @@ #include <ec/ec.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -47,7 +46,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index ef1acbd..257b8fa 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -8,7 +8,6 @@ #include <soc/gpio.h> #include <soc/int15.h> #include <bootstate.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(struct device *dev) { @@ -54,7 +53,6 @@ { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; /* Install custom int15 handler for VGA OPROM */ if (CONFIG(VGA_ROM_RUN)) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index e007880..8cae959 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -12,7 +12,6 @@ #include <soc/gpio.h> #include <soc/nhlt.h> #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> @@ -125,7 +124,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 6287628..8d619db 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -5,7 +5,6 @@ #include <smbios.h> #include <soc/gpio.h> #include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG(GENERATE_SMBIOS_TABLES) /* mainboard silk screen shows DIMM-A and DIMM-B */ @@ -46,12 +45,6 @@ gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 90f28e7..47f071c 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -6,7 +6,6 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -66,7 +65,6 @@ { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 7f4e29d2..ae68a78 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -6,7 +6,6 @@ #include <acpi/acpi.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/quanta/it8518/ec.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -42,7 +41,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 9f8e646..892da51 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -14,7 +14,6 @@ #include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> #include <vb2_api.h> @@ -78,7 +77,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->get_smbios_strings = mainboard_smbios_strings; variant_ramstage_init(); diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index ea292f1..54da830 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -23,7 +23,6 @@ #include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <commonlib/helpers.h> #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" @@ -203,7 +202,6 @@ /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; } diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index 904673e..f929b10 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -6,7 +6,6 @@ #include <drivers/intel/gma/opregion.h> #include <ec/ec.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <smbios.h> #include <stdint.h> #include <string.h> @@ -57,8 +56,6 @@ static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; - #if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) dev->ops->get_smbios_strings = mainboard_smbios_strings; #endif diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 04803fa..73fa9aa 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -5,7 +5,6 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -18,7 +17,6 @@ static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index aa073bc..eb9a316 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -6,7 +6,6 @@ #include <nhlt.h> #include <soc/gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) { @@ -45,7 +44,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 6291d60..3b6727b 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -4,14 +4,12 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index cfbaf0d..1cfa4e0 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -9,7 +9,6 @@ #include <nhlt.h> #include <soc/gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/ec.h> #include <variant/gpio.h> @@ -55,7 +54,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index c8e9e41..2440651 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -5,7 +5,6 @@ #include <baseboard/variants.h> #include <device/device.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) { @@ -16,12 +15,6 @@ gpio_configure_pads(pads, num); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 315d47d..efba386 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -7,7 +7,6 @@ #include <soc/gpio.h> #include <soc/pcr_ids.h> #include <smbios.h> -#include <vendorcode/google/chromeos/chromeos.h> #define SERIAL_IO_PCR_GPPRVRW4 0x60C @@ -23,11 +22,6 @@ pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - const char *smbios_system_sku(void) { static const char *sku_str = "sku2147483647"; /* sku{0-1} */ @@ -36,5 +30,4 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index e502d846..2b09df4 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include <variant/gpio.h> @@ -21,7 +20,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 4136c36..b7c61f5 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <gpio.h> #include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "gpio.h" @@ -82,7 +81,6 @@ { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/shadowmountain/mainboard.c b/src/mainboard/intel/shadowmountain/mainboard.c index 2783b4d..f035aa9 100644 --- a/src/mainboard/intel/shadowmountain/mainboard.c +++ b/src/mainboard/intel/shadowmountain/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <ec/ec.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) { @@ -21,12 +20,6 @@ mainboard_ec_init(); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 82f4629..447ae31 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(struct device *dev) @@ -17,7 +16,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 82877ed..bbce927 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <ec/ec.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <smbios.h> #include <string.h> @@ -29,12 +28,6 @@ mainboard_ec_init(); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index e9583ac..d17645f 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -2,14 +2,12 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index d804b2b..9bf3b96 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -10,7 +10,6 @@ #include "onboard.h" #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> -#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -73,7 +72,6 @@ { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 6291d60..3b6727b 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -4,14 +4,12 @@ #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 500e632..5a54d70 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -33,8 +33,3 @@ acpigen_pop_len(); } - -void chromeos_dsdt_generator(const struct device *dev) -{ - mainboard_chromeos_acpi_generate(); -} diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 456f2d7..b9f807f 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -97,4 +97,6 @@ } } +#include <vendorcode/google/chromeos/acpi/gnvs.asl> + #include "ramoops.asl" diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 89e7055..7be4586 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This is the ChromeOS specific ACPI information needed by - * the mainboard's chromeos.asl + * chromeos.asl */ +External (CNVS, OpRegionObj) + Field (CNVS, ByteAcc, NoLock, Preserve) { VBT0, 32, // 0x000 - Boot Reason diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 730a4bb..abdd6c2 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -26,6 +26,7 @@ void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); void chromeos_set_ecfw_rw(void); +void chromeos_init_chromeos_acpi(void); /** * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD @@ -45,16 +46,9 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); /* - * Common helper function and delcarations for mainboards to use to generate - * ACPI-specific Chrome OS needs. + * Declaration for mainboards to use to generate ACPI-specific Chrome OS needs. */ void mainboard_chromeos_acpi_generate(void); -#if CONFIG(CHROMEOS) -struct device; -void chromeos_dsdt_generator(const struct device *dev); -#else -#define chromeos_dsdt_generator NULL -#endif enum { CROS_GPIO_REC = 1, /* Recovery */ diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 531463b..7236662 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -98,7 +98,14 @@ { const struct opregion cnvs_op = OPREGION("CNVS", SYSTEMMEMORY, (uintptr_t)chromeos_acpi, sizeof(*chromeos_acpi)); + + if (!chromeos_acpi) + return; + acpigen_write_scope("\\"); acpigen_write_opregion(&cnvs_op); acpigen_pop_len(); + + /* Usually this creates OIPG package for GPIOs. */ + mainboard_chromeos_acpi_generate(); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index a25b2b0..a9f93d9 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -32,6 +32,4 @@ u8 pad[298]; // dd6-eff } __packed; -void chromeos_init_chromeos_acpi(void); - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 19 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/taniks: Include driver for GL9763E for eMMC boot disk
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60023 ) Change subject: mb/google/brya/var/taniks: Include driver for GL9763E for eMMC boot disk ...................................................................... mb/google/brya/var/taniks: Include driver for GL9763E for eMMC boot disk Support GL9763E as a eMMC boot disk BUG=b:210089379 TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taniks. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Iab0fd88ac88e07a8580426234adc9c21df6c11d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60023 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 9f7f75a..bf1f5f9 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -134,3 +134,4 @@ config BOARD_GOOGLE_TANIKS bool "-> Taniks" select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9763E -- To view, visit https://review.coreboot.org/c/coreboot/+/60023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab0fd88ac88e07a8580426234adc9c21df6c11d6 Gerrit-Change-Number: 60023 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brask: Customize LEDs of RT8125
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60298 ) Change subject: mb/google/brya/var/brask: Customize LEDs of RT8125 ...................................................................... mb/google/brya/var/brask: Customize LEDs of RT8125 Add Kconfig item RT8168_SET_LED_MODE to enable LED customization. Update the LED settings in devicetree. BUG=b:193750191 TEST=Try different register values to verify LED feature. Signed-off-by: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Change-Id: If80ace497c7481ce40b55af7e17e12a286aa9164 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60298 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9363d6e..fa618b9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -9,6 +9,7 @@ select SPD_CACHE_IN_FMAP select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE select RT8168_GEN_ACPI_POWER_RESOURCE if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index fbb64ff..9a0e073 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -96,6 +96,9 @@ register "stop_off_delay_ms" = "1" register "has_power_resource" = "1" register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" device pci 00.0 on end end end # RTL8125 Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/60298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80ace497c7481ce40b55af7e17e12a286aa9164 Gerrit-Change-Number: 60298 Gerrit-PatchSet: 3 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/net/r8168: Modify to support RTL8125 LEDs
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59531 ) Change subject: drivers/net/r8168: Modify to support RTL8125 LEDs ...................................................................... drivers/net/r8168: Modify to support RTL8125 LEDs The Realtek RTL8125 has four registers for four leds and a feature config register. We use led0 and led2 in brask, so modify ethernet driver. Those registers' IO address are based on RTL8125 datasheet. BUG=b:193750191 TEST=Modify overridetree.cb to verify LEDs' settings. Signed-off-by: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59531 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/net/chip.h M src/drivers/net/r8168.c 2 files changed, 69 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 9b6a4e5..a4ba8af 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -8,6 +8,11 @@ struct drivers_net_config { uint16_t customized_leds; + /* RTL8125 LED settings */ + uint8_t led_feature; + uint16_t customized_led0; + uint16_t customized_led2; + unsigned int wake; /* Wake pin for ACPI _PRW */ /* Does the device have a power resource? */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 5606859..2299a99 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -29,6 +29,9 @@ #define CMD_REG 0x37 #define CMD_REG_RESET 0x10 #define CMD_LED0_LED1 0x18 +#define CMD_LED_FEATURE 0x94 +#define CMD_LEDSEL0 0x18 +#define CMD_LEDSEL2 0x84 #define CFG_9346 0x50 #define CFG_9346_LOCK 0x00 @@ -249,28 +252,69 @@ if (!config) return; - /* Read the customized LED setting from devicetree */ - printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds); + if (dev->device == PCI_DEVICE_ID_REALTEK_8125) { + /* Set LED global Feature register */ + outb(config->led_feature, io_base + CMD_LED_FEATURE); + printk(BIOS_DEBUG, "r8125: read back LED global feature setting as 0x%x\n", + inb(io_base + CMD_LED_FEATURE)); - /* - * Refer to RTL8111H datasheet 7.2 Customizable LED Configuration - * Starting from offset 0x18 - * Bit[15:12] LED Feature Control(FC) - * Bit[11:08] LED Select for PINLED2 - * Bit[07:04] LED Select for PINLED1 - * Bit[03:00] LED Select for PINLED0 - * - * Speed Link10M Link100M Link1000M ACT/Full - * LED0 Bit0 Bit1 Bit2 Bit3 - * LED1 Bit4 Bit5 Bit6 Bit7 - * LED2 Bit8 Bit9 Bit10 Bit11 - * FC Bit12 Bit13 Bit14 Bit15 - */ + /* + * Refer to RTL8125 datasheet 5.Customizable LED Configuration + * Register Name IO Address + * LEDSEL0 0x18 + * LEDSEL2 0x84 + * LEDFEATURE 0x94 + * + * LEDSEL Bit[] Description + * Bit0 Link10M + * Bit1 Link100M + * Bit3 Link1000M + * Bit5 Link2.5G + * Bit9 ACT + * Bit10 preboot enable + * Bit11 lp enable + * Bit12 active low/high + * + * LEDFEATURE Description + * Bit0 LED Table V1/V2 + * Bit1~3 Reserved + * Bit4~5 LED Blinking Duty Cycle 12.5%/ 25%/ 50%/ 75% + * Bit6~7 LED Blinking Freq. 240ms/160ms/80ms/Link-Speed-Dependent + */ - /* Set customized LED registers */ - outw(config->customized_leds, io_base + CMD_LED0_LED1); - printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", - inw(io_base + CMD_LED0_LED1)); + /* Set customized LED0 register */ + outw(config->customized_led0, io_base + CMD_LEDSEL0); + printk(BIOS_DEBUG, "r8125: read back LED0 setting as 0x%x\n", + inw(io_base + CMD_LEDSEL0)); + + /* Set customized LED2 register */ + outw(config->customized_led2, io_base + CMD_LEDSEL2); + printk(BIOS_DEBUG, "r8125: read back LED2 setting as 0x%x\n", + inw(io_base + CMD_LEDSEL2)); + } else { + /* Read the customized LED setting from devicetree */ + printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds); + + /* + * Refer to RTL8111H datasheet 7.2 Customizable LED Configuration + * Starting from offset 0x18 + * Bit[15:12] LED Feature Control(FC) + * Bit[11:08] LED Select for PINLED2 + * Bit[07:04] LED Select for PINLED1 + * Bit[03:00] LED Select for PINLED0 + * + * Speed Link10M Link100M Link1000M ACT/Full + * LED0 Bit0 Bit1 Bit2 Bit3 + * LED1 Bit4 Bit5 Bit6 Bit7 + * LED2 Bit8 Bit9 Bit10 Bit11 + * FC Bit12 Bit13 Bit14 Bit15 + */ + + /* Set customized LED registers */ + outw(config->customized_leds, io_base + CMD_LED0_LED1); + printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", + inw(io_base + CMD_LED0_LED1)); + } } static void r8168_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/59531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92 Gerrit-Change-Number: 59531 Gerrit-PatchSet: 7 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/hatch: Move selects from Kconfig.name to Kconfig
by Felix Singer (Code Review) 23 Dec '21

23 Dec '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60155 ) Change subject: mb/google/hatch: Move selects from Kconfig.name to Kconfig ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > phew lots of moves but looks correct Every patch represents a single step. In such changes I copy&paste the options, then I remove the type declarations from Kconfig and then I remove the selects from Kconfig.name. Thanks a lot for your reviews! -- To view, visit https://review.coreboot.org/c/coreboot/+/60155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb7fcaaa175eb5b6e953ad0d5e2c5757d18838e4 Gerrit-Change-Number: 60155 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 20:53:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Add Hynix LP5 DRAM support
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60288 ) Change subject: mb/google/brya/var/vell: Add Hynix LP5 DRAM support ...................................................................... mb/google/brya/var/vell: Add Hynix LP5 DRAM support Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell: DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/memory/Makefile.inc M src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc index 8288400..05f4689 100644 --- a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc @@ -5,4 +5,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B -SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt index f029f6b..2e3eb01 100644 --- a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt @@ -6,3 +6,4 @@ DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) +H9JCNNNCP3MLYR-N6E 1 (0001) diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt index 3baf5d4..f81efc5 100644 --- a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt @@ -11,3 +11,4 @@ # Part Name MT62F512M32D2DR-031 WT:B MT62F1G32D4DR-031 WT:B +H9JCNNNCP3MLYR-N6E -- To view, visit https://review.coreboot.org/c/coreboot/+/60288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Gerrit-Change-Number: 60288 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brask: Update PL and PsysPL
by Tim Wawrzynczak (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: V Sowmya, Kane Chen, Curtis Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60323 ) Change subject: mb/google/brya/var/brask: Update PL and PsysPL ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/60323/comment/28b2d356_06dbad0c PS2, Line 20: { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, for another change: these last few are out of order -- To view, visit https://review.coreboot.org/c/coreboot/+/60323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a827ae40e26294db20d5d1b2121dcce5118e290 Gerrit-Change-Number: 60323 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 20:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Initialize display signals on user mode
by Tim Wawrzynczak (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: shkim, Henry Sun, Evan Green, Paul Menzel, Simon Yang, Edward Doan, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60190 ) Change subject: mb/google/dedede/var/bugzzy: Initialize display signals on user mode ...................................................................... Patch Set 13: Code-Review+2 (1 comment) File src/mainboard/google/dedede/variants/bugzzy/ramstage.c: https://review.coreboot.org/c/coreboot/+/60190/comment/e77e60cc_1ca47b6b PS13, Line 61: Verified-1 is coming from the extra newline here. -- To view, visit https://review.coreboot.org/c/coreboot/+/60190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db Gerrit-Change-Number: 60190 Gerrit-PatchSet: 13 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 20:15:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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