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Change subject: mb/google/corsola: Fully calibrate DRAM
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60386/comment/8f7d33e9_fe355568
PS3, Line 9: Initialize and calibrate DRAM in romstage.
> No, if we not do full dram calibration, the stage will pause on romstage. […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/60386/comment/53a08ec5_2e988c45
PS4, Line 13: 20014 msecs
> because we have dumped the logs, so it will cause so many time. […]
Done
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Change subject: mb/google/corsola: Initialize kingler display
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60398/comment/ad862819_3ed58174
PS4, Line 7: kingler
> Where is the kingler specific?
I modify the description to prevent misunderstanding.
"saw firmware display on eDP panel of kingler board"
https://review.coreboot.org/c/coreboot/+/60398/comment/d81e4539_34d58fb1
PS4, Line 14: TEST=see fw display on kingler panel
> Maybe paste the new log messages.
it's hard to show result of display.
I think "see fw display on kingler panel" is ok.
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60398
to look at the new patch set (#6).
Change subject: mb/google/corsola: Initialize kingler display
......................................................................
mb/google/corsola: Initialize kingler display
ANX7625 is used on Kingler board as the eDP bridge IC. Enable ANX7625
and configure display in mainboard_init() to support display in
firmware screen.
BUG=b:209930699
TEST=saw firmware display on eDP panel of kingler board.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91
---
M src/mainboard/google/corsola/Kconfig
M src/mainboard/google/corsola/Makefile.inc
A src/mainboard/google/corsola/display.c
A src/mainboard/google/corsola/display.h
M src/mainboard/google/corsola/gpio.h
M src/mainboard/google/corsola/mainboard.c
6 files changed, 145 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/60398/6
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 )
Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
......................................................................
Patch Set 71:
(1 comment)
File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/comment/f36d43f4_11cd4c2a
PS67, Line 12: # SPS doesn't support all commands issued by FSP
> Well, it's not required, but saves some time
Ack
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60396 )
Change subject: soc/mediatek/mt8186: Add DDP driver
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60396/comment/d4812618_e60703ba
PS3, Line 11:
> Is there a Linux kernel driver, and are they quite similar?
yes, we implement ddp in gpu/drm/mediatek.
the main path is the same.
File src/soc/mediatek/mt8186/ddp.c:
https://review.coreboot.org/c/coreboot/+/60396/comment/7042a2e2_e120dc07
PS3, Line 13: * POSTMASK0->DITHER->DSI0
> Fits on the line above?
Done
https://review.coreboot.org/c/coreboot/+/60396/comment/8024eeeb_b41378c6
PS3, Line 136: /* Turn off M4U port. */
> Remove dot/period at the end?
Done
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Change subject: mb/google/corsola: Fully calibrate DRAM
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60386/comment/f4337632_c80d90b5
PS3, Line 9: Initialize and calibrate DRAM in romstage.
> Without full calibration (basic(?)), did the board boot?
No, if we not do full dram calibration, the stage will pause on romstage.
Because we failed to do dram calibration, dram will failed to be used and will not
go to ramstage.
Commit Message:
https://review.coreboot.org/c/coreboot/+/60386/comment/4e30c30c_02e70d64
PS4, Line 13: 20014 msecs
> That’s 20 seconds, wow! […]
because we have dumped the logs, so it will cause so many time.
If we close uart dump, it will be a proper number.
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