coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/common/cse: Helper function to set D0I3 for all HECI devices
by Arthur Heymans (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60404 ) Change subject: soc/intel/common/cse: Helper function to set D0I3 for all HECI devices ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/60404/comment/9d7320e9_5b72f68b PS2, Line 17: /* SoC callback to set D0I3 for all HECI devices */ : __weak void soc_heci_set_d0i3(void) { /* no-op */ } Is the weak empty function meaningful on most SoC's or should it be implemented by all and this is just a placeholder? -- To view, visit https://review.coreboot.org/c/coreboot/+/60404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9eb573be096928ccd6cd05b672ec022f5840059 Gerrit-Change-Number: 60404 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 22:47:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode
by Subrata Banik (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60407 ) Change subject: soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode ...................................................................... soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode Since TGL `spi_protection_mode` bit replaces the previous `manufacturing mode` without changing the offset and purpose of this bit. This patch renames to `mfg_mode` to maintain the parity with other PCHs as part of IA-common code. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 --- M src/soc/intel/alderlake/include/soc/me.h M src/soc/intel/alderlake/me.c M src/soc/intel/elkhartlake/include/soc/me.h M src/soc/intel/elkhartlake/me.c M src/soc/intel/tigerlake/include/soc/me.h M src/soc/intel/tigerlake/me.c 6 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/60407/1 diff --git a/src/soc/intel/alderlake/include/soc/me.h b/src/soc/intel/alderlake/include/soc/me.h index 993a3bc..8eea095 100644 --- a/src/soc/intel/alderlake/include/soc/me.h +++ b/src/soc/intel/alderlake/include/soc/me.h @@ -10,7 +10,7 @@ u32 data; struct { u32 working_state: 4; - u32 spi_protection_mode: 1; + u32 mfg_mode: 1; u32 fpt_bad: 1; u32 operation_state: 3; u32 fw_init_complete: 1; diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index da1a299..ea94902 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -121,14 +121,14 @@ * production system to indicate ME Manufacturing mode is disabled. */ printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - ((hfsts1.fields.spi_protection_mode == 0) && + ((hfsts1.fields.mfg_mode == 0) && (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); /* * The SPI Protection Mode bit reflects SPI descriptor * locked(0) or unlocked(1). */ printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", - hfsts1.fields.spi_protection_mode ? "NO" : "YES"); + hfsts1.fields.mfg_mode ? "NO" : "YES"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", diff --git a/src/soc/intel/elkhartlake/include/soc/me.h b/src/soc/intel/elkhartlake/include/soc/me.h index 8d1021f..d845629 100644 --- a/src/soc/intel/elkhartlake/include/soc/me.h +++ b/src/soc/intel/elkhartlake/include/soc/me.h @@ -8,7 +8,7 @@ uint32_t data; struct { uint32_t working_state: 4; - uint32_t spi_protection_mode: 1; + uint32_t mfg_mode: 1; uint32_t fpt_bad: 1; uint32_t operation_state: 3; uint32_t fw_init_complete: 1; diff --git a/src/soc/intel/elkhartlake/me.c b/src/soc/intel/elkhartlake/me.c index 5087781..cb70d50 100644 --- a/src/soc/intel/elkhartlake/me.c +++ b/src/soc/intel/elkhartlake/me.c @@ -32,7 +32,7 @@ printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); printk(BIOS_DEBUG, "ME: SPI Protection Mode : %s\n", - hfsts1.fields.spi_protection_mode ? "YES" : "NO"); + hfsts1.fields.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index 674ac7e..ed25444 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -8,7 +8,7 @@ u32 data; struct { u32 working_state: 4; - u32 spi_protection_mode: 1; + u32 mfg_mode: 1; u32 fpt_bad: 1; u32 operation_state: 3; u32 fw_init_complete: 1; diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index da1a299..ea94902 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -121,14 +121,14 @@ * production system to indicate ME Manufacturing mode is disabled. */ printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - ((hfsts1.fields.spi_protection_mode == 0) && + ((hfsts1.fields.mfg_mode == 0) && (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); /* * The SPI Protection Mode bit reflects SPI descriptor * locked(0) or unlocked(1). */ printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", - hfsts1.fields.spi_protection_mode ? "NO" : "YES"); + hfsts1.fields.mfg_mode ? "NO" : "YES"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/60407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 Gerrit-Change-Number: 60407 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Subrata Banik (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60405 to look at the new patch set (#2). Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... soc/intel/common/cse: Implement HECI notify This patch implements required heci operation to perform prior to booting to OS after platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_eop.c 2 files changed, 76 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Helper API to know CSE SPI Protection Mode
by Subrata Banik (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60403 to look at the new patch set (#2). Change subject: soc/intel/common/cse: Helper API to know CSE SPI Protection Mode ...................................................................... soc/intel/common/cse: Helper API to know CSE SPI Protection Mode This patch checks CSE's spi protection mode is protected or unprotected. Returns true if CSE's spi protection mode is protected, otherwise false. BUG=b:211954778 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/60403/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca Gerrit-Change-Number: 60403 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
by Subrata Banik (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60402 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional ...................................................................... drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional The FSP API used to notify the FSP about different phases in the boot process. The current FSP specification support three notify phases: - Post PCI enumeration - Ready to Boot - End of Firmware This patch attempts to make FSP Notify Phase APIs optional by using native coreboot implementation to perform the required lock down and chipset register configuration prior boot to payload. BUG=b:211954778 TEST=Able to build brya without any compilation issue. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/notify.c 2 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60402/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 Gerrit-Change-Number: 60402 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting
by Paul Menzel (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Kenneth Chan, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60328 ) Change subject: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60328/comment/88f70567_86fb3262 PS1, Line 9: Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt. > For correctness, unused with dewatt chematics. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If449453bc60ed41e104346429babc06a73acef64 Gerrit-Change-Number: 60328 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 16:34:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting
by Rob Barnes (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Paul Menzel, Kenneth Chan, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60328 ) Change subject: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If449453bc60ed41e104346429babc06a73acef64 Gerrit-Change-Number: 60328 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 27 Dec 2021 15:51:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by build bot (Jenkins) (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... Patch Set 1: (3 comments) File src/soc/intel/common/block/cse/cse_eop.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136350): https://review.coreboot.org/c/coreboot/+/60405/comment/ca2963b7_71b9ac79 PS1, Line 203: * BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3) prior to line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136350): https://review.coreboot.org/c/coreboot/+/60405/comment/a2535098_18cd27bb PS1, Line 234: if (!is_cse_devfn_visible(PCH_DEVFN_CSE)) suspect code indent for conditional statements (8, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136350): https://review.coreboot.org/c/coreboot/+/60405/comment/3a113e2b_56ba04e1 PS1, Line 252: /* Step 3: If devicetree.cb policy is set to disabled, then hide CSE prior to boot */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 27 Dec 2021 15:48:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs
by Subrata Banik (Code Review) 27 Dec '21

27 Dec '21

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Subrata Banik (Code Review) 27 Dec '21

27 Dec '21

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... soc/intel/common/cse: Implement HECI notify This patch implements required heci operation to perform prior to booting to OS after platform decides to skip FSP notify APIsi.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_eop.c 2 files changed, 73 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index ec901ca..4dff215 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -5,6 +5,15 @@ Driver for communication with Converged Security Engine (CSE) over Host Embedded Controller Interface (HECI) +config SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY + bool + default n + select SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT + select SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + help + Use this config to perform required heci notify by native coreboot + CSE driver instead calling FSP Notify APIs. + config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM bool default y if HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 9ae0fdf..d56f0c7 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -4,9 +4,11 @@ #include <console/console.h> #include <intelblocks/cse.h> #include <intelblocks/pmc_ipc.h> +#include <intelblocks/pmclib.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> #include <soc/pci_devs.h> +#include <soc/soc_chip.h> #include <timestamp.h> #include <types.h> @@ -188,6 +190,25 @@ } } +static void perform_lock_config(void) +{ + /* + * As per ME BWG recommendation the BIOS should not lock down CF9GR bit during + * manufacturing and re-manufacturing environment if HFSTS1 [4] is set. + */ + if ((cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable()) && + cse_is_hfs1_spi_protected()) { + /* + * Make sure payload/OS can't trigger global reset. + * BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3) prior to + * transferring control to the OS. + */ + pmc_global_reset_disable_and_lock(); + } else { + pmc_global_reset_enable(false); + } +} + static void set_cse_end_of_post(void *unused) { /* @@ -208,6 +229,48 @@ set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); } +static void cse_set_to_d0i3(void) +{ + if (!is_cse_devfn_visible(PCH_DEVFN_CSE)) + return; + + set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); +} + +static void perform_heci_notify(void *unused) +{ + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY)) + return; + + /* Step 1: Send EOP to CSE */ + set_cse_end_of_post(NULL); + + if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) { + /* Step 2: Perform lock config */ + perform_lock_config(); + + /* Step 3: If devicetree.cb policy is set to disabled, then hide CSE prior to boot */ + const config_t *conf = config_of_soc(); + + if (!conf->HeciEnabled) { + cse_set_to_d0i3(); + cse_disable_mei_devices(); + } + } + + /* Step 4: Setting D0I3 bits for HECI devices */ + if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + soc_heci_set_d0i3(); +} + +/* + * Perform HECI notify function when platform selects SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY + * that includes sending EOP, lock configuration and put heci to D0i3 etc. Associate + * this operation with BS_PAYLOAD_BOOT to ensure its almost the last operation prior + * to loading payload. + */ +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, perform_heci_notify, NULL); + /* * Ideally, to give coreboot maximum flexibility, sending EOP would be done as * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must @@ -217,7 +280,7 @@ * Otherwise, EOP can be pushed a little later, and can be performed in * BS_PAYLOAD_BOOT instead. */ -#if !CONFIG(HECI_DISABLE_USING_SMM) +#if !CONFIG(HECI_DISABLE_USING_SMM) && !CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY) BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL); #else BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021