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Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60277 )
Change subject: mb/google/brya/var/gimble: Update Slow Slew Rate
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi Tim,
Please help to review it, thanks.
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60405
to look at the new patch set (#5).
Change subject: soc/intel/common/cse: Implement HECI notify
......................................................................
soc/intel/common/cse: Implement HECI notify
This patch implements required heci operation to perform
prior to booting to OS after platform decides to skip FSP
notify APIs i.e. Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with
this code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY:
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_eop.c
2 files changed, 85 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/5
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Andrey Petrov, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60402
to look at the new patch set (#3).
Change subject: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
......................................................................
drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
The FSP API used to notify the FSP about different phases
in the boot process. The current FSP specification support
three notify phases:
- Post PCI enumeration
- Ready to Boot
- End of Firmware
This patch attempts to make FSP Notify Phase APIs optional
by using native coreboot implementation to perform the
required lock down and chipset register configuration prior
boot to payload.
BUG=b:211954778
TEST=Able to build brya without any compilation issue and coreboot
log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled.
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/notify.c
2 files changed, 53 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60402/3
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60401 )
Change subject: soc/intel/alderlake: Check clkreq overlap
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/60401/comment/deedd9ef_e50fd75b
PS2, Line 31: static u32 clk_req_mapping = 0;
can we keep this at line #57 below ? anyway you have defined as `static`
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Change subject: IASL: Ignore IASL's "Missing dependency" warning
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> How to automatically check if something* is missing or wrong?
I'm not sure if my English is clear 😊
the idea is if we disable a specific warning for existing code, we are also blindly disabling it for any new incoming code.
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Change subject: soc/intel/alderlake: Check clkreq overlap
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: IASL: Ignore IASL's "Missing dependency" warning
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Let say current coreboot ASL code is correct, so we can disable this warning for existing ASL code. […]
How to automatically check if something* is missing or wrong?
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Change subject: IASL: Ignore IASL's "Missing dependency" warning
......................................................................
Patch Set 5:
(2 comments)
Patchset:
PS5:
> maybe we can remove the need for this CONFIG instead? […]
Let say current coreboot ASL code is correct, so we can disable this warning for existing ASL code. But what about new incoming asl codes? How to automatically check if some this is missing or wrong?
Should we drop “-we” option and remove all IGNORE_IASL_* from Makefile.inc and then issue a msg to the developer to check the new asl code?
PS5:
Thx
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Change subject: mb/google/brya/var/vell: update overridetree for DP
......................................................................
Patch Set 9: Code-Review+1
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60405
to look at the new patch set (#4).
Change subject: soc/intel/common/cse: Implement HECI notify
......................................................................
soc/intel/common/cse: Implement HECI notify
This patch implements required heci operation to perform
prior to booting to OS after platform decides to skip FSP
notify APIs i.e. Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_eop.c
2 files changed, 85 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/4
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Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
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