coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: mb/google/octopus: Move selects from Kconfig.name to Kconfig
by Kyösti Mälkki (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60344 ) Change subject: mb/google/octopus: Move selects from Kconfig.name to Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5949fc474c4923beb1f41a40876f03e5c70fc5b1 Gerrit-Change-Number: 60344 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Tue, 28 Dec 2021 10:24:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
by Felix Singer (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Andrey Petrov, Patrick Rudolph, EricR Lai. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60402 ) Change subject: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60402/comment/635960c0_76262ee1 PS2, Line 9: used *is* used -- To view, visit https://review.coreboot.org/c/coreboot/+/60402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 Gerrit-Change-Number: 60402 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 28 Dec 2021 10:24:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/octopus/Kconfig: Reorder selects alphabetically
by Kyösti Mälkki (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60343 ) Change subject: mb/google/octopus/Kconfig: Reorder selects alphabetically ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I545a1111e24f45f732f1c325c808737dfb6bcae6 Gerrit-Change-Number: 60343 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Dec 2021 10:22:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/cse: Helper function to set D0I3 for all HECI devices
by Arthur Heymans (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60404 ) Change subject: soc/intel/common/cse: Helper function to set D0I3 for all HECI devices ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/60404/comment/7f9cdc4a_f656c4d8 PS2, Line 17: /* SoC callback to set D0I3 for all HECI devices */ : __weak void soc_heci_set_d0i3(void) { /* no-op */ } > > Is the weak empty function meaningful on most SoC's or should it be implemented by all and this is just a placeholder? > > Ideally should be implemented by other SoC and this is just a placeholder. For example: https://review.coreboot.org/c/coreboot/+/60406/2/src/soc/intel/alderlake/fi… > > I wished to make this mandatory for SoC that selects SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY (skips FSP Notify APIs hence, coreboot need to put HECI devices into D0i3) but in that case we might need to guard function declaration as well. WDYT about this ? I think it's best to avoid weak function as placeholders in this case. If you forgot about it (e.g. a future SoC) you'd have to find why it's not working at runtime. If there is a declaration without a definition, the compiler will pinpoint you towards the problem, before you even ran the image. Why should the declaration be guarded? Only the function call needs to be. if (CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY)) soc_heci_set_d0i3() should work fine. Making a definition mandatory would be my preference. -- To view, visit https://review.coreboot.org/c/coreboot/+/60404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9eb573be096928ccd6cd05b672ec022f5840059 Gerrit-Change-Number: 60404 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 28 Dec 2021 09:41:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next build
by Kevin Chang (Code Review) 28 Dec '21

28 Dec '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, YH Lin. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60330 ) Change subject: mb/google/brya/var/taeko: swap TPM i2c with TS i2c for the next build ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60330/comment/ea35476d_fecbddeb PS2, Line 9: Taeko will > 1. Do the schematics have revisions? […] 1. Yes, this change is follow Brya. 2. Update in latest patchset. -- To view, visit https://review.coreboot.org/c/coreboot/+/60330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d Gerrit-Change-Number: 60330 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Dec 2021 09:38:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Prevent passing NULL MIPI commands
by Felix Held (Code Review) 28 Dec '21

28 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60392 ) Change subject: soc/mediatek: Prevent passing NULL MIPI commands ...................................................................... soc/mediatek: Prevent passing NULL MIPI commands Previously (before CB:56965 [1]) mtk_dsi_send_init_command() would ignore NULL initialization commands passed to it. However, in the current code mipi_panel_parse_init_commands() doesn't check that (see CB:57150 [2]), so we should check it on the caller side from mtk_dsi_init(). [1] b2a1480191 device: Move MIPI panel library from mainboard/google/kukui into common [2] 4757a7ea33 mipi: Make panel init callback work directly on DSI transaction types BUG=b:202871018, b:209930699 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60392 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/common/dsi.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index a4556f5..f16d8f2 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -377,7 +377,8 @@ mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_clk_hs_mode_enable(); - mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq); + if (init_commands) + mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq); mtk_dsi_set_mode(mode_flags); mtk_dsi_start(); -- To view, visit https://review.coreboot.org/c/coreboot/+/60392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c Gerrit-Change-Number: 60392 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Enable VRF12 software control for MT6366
by Felix Held (Code Review) 28 Dec '21

28 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60340 ) Change subject: soc/mediatek/mt8186: Enable VRF12 software control for MT6366 ...................................................................... soc/mediatek/mt8186: Enable VRF12 software control for MT6366 PS8640 is a low power MIPI-to-eDP video format converter. VRF12 does not provide power to PS8640 on krabby. In original patch, VRF12 is not used, and is set to hardware control for low power. We change the setting to remove hardware control. Therefore, if we want to control VRF12 by software, we can control it directly. BUG=b:210806060 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60340 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 450b783..5cec47a 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -211,10 +211,6 @@ {0x1C1E, 0x1, 0x1, 2}, /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ {0x1C24, 0x0, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ - {0x1C32, 0x1, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ - {0x1C38, 0x0, 0x1, 2}, /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ {0x1C46, 0x1, 0x1, 0}, /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ @@ -325,10 +321,6 @@ {0x1C1E, 0x1, 0x1, 2}, /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ {0x1C24, 0x0, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ - {0x1C32, 0x1, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ - {0x1C38, 0x0, 0x1, 2}, /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ {0x1C46, 0x1, 0x1, 0}, /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549 Gerrit-Change-Number: 60340 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add devapc basic drivers
by Felix Held (Code Review) 28 Dec '21

28 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60317 ) Change subject: soc/mediatek/mt8186: Add devapc basic drivers ...................................................................... soc/mediatek/mt8186: Add devapc basic drivers Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set default permission. BUG=b:202871018 TEST=build pass Signed-off-by: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60317 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/devapc.c A src/soc/mediatek/mt8186/include/soc/devapc.h M src/soc/mediatek/mt8186/soc.c 4 files changed, 1,421 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 2a22e6e..5d3f668 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -40,6 +40,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += ../common/auxadc.c +ramstage-y += devapc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8186/devapc.c b/src/soc/mediatek/mt8186/devapc.c new file mode 100644 index 0000000..2f86501 --- /dev/null +++ b/src/soc/mediatek/mt8186/devapc.c @@ -0,0 +1,1325 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is created based on MT8169_DEVICE_APC_REG_DEVAPC_external.docx */ + +#include <console/console.h> +#include <soc/devapc.h> +#include <soc/devapc_common.h> + +static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = { + /* 0 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPCKGEN", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_INFRASYS_CONFIG_REGS", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("IO_CFG_REG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ PERICFG", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_EFUSAO_DEBUG", + SEC_RW_NS_R, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_GPIO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SLEEP_CONTROLLER", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPRGU", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APXGPT", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_RESERVE", + NO_PROTECTION, FORBIDDEN7), + + /* 10 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SEJ", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AP_CIRQ_EINT", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APMIXEDSYS", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIC_WRAP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_INFRA_PERI", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MM", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_KEYPAD", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOP_MISC", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ DVFS_CTRL_PROC", + NO_PROTECTION, SEC_RW_NS_R, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_IFNRA_TOP_MBIST_CTRL", + NO_PROTECTION, FORBIDDEN7), + + /* 20 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DPMAIF_AO_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AES_TOP_0", + FORBIDDEN, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SYS_TIMER", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MDEM_TEMP_SHARE", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MD", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SECURITY_AO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPMI_MST_WRAP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + + /* 30 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_AP_DMA", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SYS_CIRQ", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICAPC", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBG_TRACKER", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + + /* 40 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_INFRA_PDN_REGISTER", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_TRNG", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DX_CC", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN, + NO_PROTECTION, FORBIDDEN4), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CQ_DMA", + NO_PROTECTION, FORBIDDEN7), + + /* 50 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, + NO_PROTECTION, FORBIDDEN4), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SRAMROM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICMPU_LOW", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI_MPU_REG", + SEC_RW_NS_R, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + + /* 60 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP1", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP2", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP4", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP6", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + + /* 70 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_GCE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP0", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP1", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP2", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP4", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP6", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + + /* 80 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_AP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_1", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_2", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_2", + SEC_RW_NS_R, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_4", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_6", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + + /* 90 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_7", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_8", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SCP", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MCUCFG(*)", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBUGSYS", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUXADC", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART0", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C7", + NO_PROTECTION, FORBIDDEN7), + + /* 100 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C8", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PWM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PTP", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_BTIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C6", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_DISP_PWM", + NO_PROTECTION, FORBIDDEN7), + + /* 110 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C4", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI4", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI5", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C5", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_IMP_IIC_WRAP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART2", + NO_PROTECTION, FORBIDDEN7), + + /* 120 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C9", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN5, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SUB", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UFS", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF2", + NO_PROTECTION, FORBIDDEN7), + + /* 130 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SIF(**)", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIO", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("EAST_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ CSI_TOP_AO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + + /* 140 */ + DAPC_INFRA_AO_SYS0_ATTR("WEST_MIPI_TX_CONFIG", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("WEST_MSDC1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("WEST_USB20_PHY", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("WEST_EFUSE", + NO_PROTECTION, SEC_RW_NS_R, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_UFS_MPHY", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_MSDC0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_CONN", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + FORBIDDEN3, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MD1", + NO_PROTECTION, FORBIDDEN7), + + /* 150 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIODSP", + NO_PROTECTION, FORBIDDEN7), +}; + +/* module, AP permission, N/A, SSPM permission, N/A */ +static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = { + + /* 0 */ + DAPC_MM_AO_SYS0_ATTR("IP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DFD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D Secure Reg", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D TestBench", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D_CONFIG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MMSYS_CONFIG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_MUTEX0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 10 */ + DAPC_MM_AO_SYS0_ATTR("SMI_COMMON", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("SMI_LARB0", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("SMI_LARB1", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("DISP_OVL0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_OVL0_2L", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_RDMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_RSZ0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_COLOR0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_CCORR0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 20 */ + DAPC_MM_AO_SYS0_ATTR("DISP_AAL0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_GAMMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_POSTMASK0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_DITHER0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_DSC_WRAP0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DSI0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_WDMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 30 */ + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("IMG1_SMI_2X1_SUB_COMMON", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 40 */ + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (mfb_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (wpe_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (mss_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 50 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("imgsys1_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 60 */ + DAPC_MM_AO_SYS0_ATTR("dip_a2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a5", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a6", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a7", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a9)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a10", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a11", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 70 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb9", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("2x1_sub_common", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mfb_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("wpe_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mss_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 80 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("imgsys2_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 90 */ + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b0)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b1)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b2)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b3)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b4)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b5)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b6)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b7)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 100 */ + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b9)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b10)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b11)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb11", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("reserved (smi_larb12)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("rserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 110 */ + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 120 */ + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0_larb", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("vdec_core0_gcon", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_mini_mdp_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("venc_global_con", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb7", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("venc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("jpgenc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 130 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("venc_mbist_ctrl", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb13", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("smi_larb14", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_a", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_c", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 140 */ + DAPC_MM_AO_SYS0_ATTR("seninf_d", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_e", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_f", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_g", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_h", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_smi_3x1_sub_common_u0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_smi_4x1_sub_common_u0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb_16", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("smi_larb_17", + NO_PROTECTION4), + + /* 150 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 160 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 170 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 180 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 190 */ + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 200 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 210 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys_a_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 220 */ + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 230 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 240 */ + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys_b_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 250 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 260 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 270 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 280 */ + DAPC_MM_AO_SYS0_ATTR("camsv_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_5", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_6", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_7", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_4_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 290 */ + DAPC_MM_AO_SYS0_ATTR("camsv_5_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_6_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_7_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("asg", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 300 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 310 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdpsys_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 320 */ + DAPC_MM_AO_SYS0_ATTR("mdp_mutex0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb0", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("mdp_rdma0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_aal0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_hdr0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_rsz0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_rsz1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_wrot0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 330 */ + DAPC_MM_AO_SYS0_ATTR("mdp_wrot1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_tdshp0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ipesys_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("fdvt", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved (fe)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("rsc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 340 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ipe_smi_2x1_sub_common", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 350 */ + DAPC_MM_AO_SYS0_ATTR("smi_larb20", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("depth", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 360 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb19", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION) +}; + +static const enum domain_id domain_map[] = { + DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3, + DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7, + DOMAIN_8, DOMAIN_9, DOMAIN_10, DOMAIN_11, + DOMAIN_12, DOMAIN_13, DOMAIN_14, DOMAIN_15, +}; + +static inline void *getreg_domain(uintptr_t base, unsigned int offset, + enum domain_id domain_id, unsigned int index) +{ + return (void *)(base + offset + domain_id * 0x100 + index * 0x4); +} + +static inline void *getreg(uintptr_t base, unsigned int offset) +{ + return getreg_domain(base, offset, 0, 0); +} + +static void set_module_apc(uintptr_t base, uint32_t module, enum domain_id domain_id, + enum devapc_perm_type perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + + apc_register_index = module / MOD_NO_IN_1_DEVAPC; + apc_set_index = module % MOD_NO_IN_1_DEVAPC; + + clrsetbits32(getreg_domain(base, 0, domain_id, apc_register_index), + 0x3 << (apc_set_index * 2), + perm << (apc_set_index * 2)); +} + +static void set_infra_ao_apc(uintptr_t base) +{ + int i, j; + + for (i = 0; i < ARRAY_SIZE(infra_ao_sys0_devices); i++) + for (j = 0; j < ARRAY_SIZE(infra_ao_sys0_devices[i].d_permission); j++) + set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], + infra_ao_sys0_devices[i].d_permission[j]); +} + +static void set_mm_ao_apc(uintptr_t base) +{ + int i, j; + + for (i = 0; i < ARRAY_SIZE(mm_ao_sys0_devices); i++) + for (j = 0; j < ARRAY_SIZE(mm_ao_sys0_devices[i].d_permission); j++) + set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], + mm_ao_sys0_devices[i].d_permission[j]); + /* + * Extra apc setting. + * Block debugsys to avoid privilege escalation. + */ + if (!CONFIG(CONSOLE_SERIAL)) + set_module_apc(base + SYS0_D0_APC_0, DEVAPC_DEBUGSYS_INDEX, + DOMAIN_0, SEC_RW_NS_R); + +} + +static void dump_infra_ao_apc(uintptr_t base) +{ + int reg_max; + unsigned int d, i; + + reg_max = DIV_ROUND_UP(ARRAY_SIZE(infra_ao_sys0_devices), MOD_NO_IN_1_DEVAPC); + for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++) + for (i = 0; i < reg_max; i++) + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: %#x\n", d, i, + read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); + + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n", + read32(getreg(base, MAS_SEC_0))); +} + +static void dump_mm_ao_apc(uintptr_t base) +{ + int reg_max; + unsigned int d, i; + + reg_max = DIV_ROUND_UP(ARRAY_SIZE(mm_ao_sys0_devices), MOD_NO_IN_1_DEVAPC); + for (d = 0; d < DOM_NUM_MM_AO_SYS0; d++) + for (i = 0; i < reg_max; i++) + printk(BIOS_DEBUG, "[DEVAPC] (MM_AO_SYS0)D%d_APC_%d: %#x\n", d, i, + read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); + + printk(BIOS_DEBUG, "[DEVAPC] (MM_AO)MAS_SEC_0: %#x\n", + read32(getreg(base, MAS_SEC_0))); +} + +static void infra_init(uintptr_t base) +{ + /* Side band */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, SECURE_TRANS); + + /* Default APC Setting */ + set_infra_ao_apc(base); +} + +static void mm_init(uintptr_t base) +{ + /* Default APC Setting */ + set_mm_ao_apc(base); +} + +struct devapc_init_ops { + uintptr_t base; + void (*init)(uintptr_t base); + void (*dump)(uintptr_t base); +} devapc_init[] = { + { DEVAPC_AO_INFRA_PERI_BASE, infra_init, dump_infra_ao_apc }, + { DEVAPC_AO_MM_BASE, mm_init, dump_mm_ao_apc }, +}; + +void dapc_init(void) +{ + unsigned int i; + uintptr_t devapc_ao_base; + + for (i = 0; i < ARRAY_SIZE(devapc_init); i++) { + devapc_ao_base = devapc_init[i].base; + + /* Init dapc */ + write32(getreg(devapc_ao_base, AO_APC_CON), 0x0); + + /* Initialization */ + if (devapc_init[i].init) + devapc_init[i].init(devapc_ao_base); + + /* Dump Setting */ + if (devapc_init[i].dump) + devapc_init[i].dump(devapc_ao_base); + } +} diff --git a/src/soc/mediatek/mt8186/include/soc/devapc.h b/src/soc/mediatek/mt8186/include/soc/devapc.h new file mode 100644 index 0000000..48d5f3e --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/devapc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is created based on MT8169_DEVICE_APC_REG_DEVAPC_external.docx */ + +#ifndef SOC_MEDIATEK_MT8186_DEVAPC_H +#define SOC_MEDIATEK_MT8186_DEVAPC_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void dapc_init(void); + +enum devapc_ao_offset { + SYS0_D0_APC_0 = 0x0, + DOM_REMAP_0_0 = 0xD00, + DOM_REMAP_1_0 = 0xD04, + MAS_DOM_0 = 0x0A00, + MAS_SEC_0 = 0x0B00, + AO_APC_CON = 0x0F00, +}; + +/****************************************************************************** + * STRUCTURE DEFINITION + ******************************************************************************/ +/* Common */ +enum trans_type { + NON_SECURE_TRANS = 0, + SECURE_TRANS, +}; + +enum devapc_perm_type { + NO_PROTECTION = 0, + SEC_RW_ONLY, + SEC_RW_NS_R, + FORBIDDEN, + PERM_NUM, +}; + +enum domain_id { + DOMAIN_0 = 0, + DOMAIN_1, + DOMAIN_2, + DOMAIN_3, + DOMAIN_4, + DOMAIN_5, + DOMAIN_6, + DOMAIN_7, + DOMAIN_8, + DOMAIN_9, + DOMAIN_10, + DOMAIN_11, + DOMAIN_12, + DOMAIN_13, + DOMAIN_14, + DOMAIN_15, +}; + +struct apc_infra_peri_dom_16 { + unsigned char d_permission[16]; +}; + +struct apc_infra_peri_dom_8 { + unsigned char d_permission[8]; +}; + +struct apc_infra_peri_dom_4 { + unsigned char d_permission[4]; +}; + +enum devapc_sys_dom_num { + DOM_NUM_INFRA_AO_SYS0 = 8, + DOM_NUM_MM_AO_SYS0 = 4, +}; + +enum devapc_cfg_index { + DEVAPC_DEBUGSYS_INDEX = 17, +}; + +/* PERM_ATTR MACRO */ +#define DAPC_INFRA_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_8(__VA_ARGS__) } } +#define DAPC_MM_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_4(__VA_ARGS__) } } + +/****************************************************************************** + * Variable DEFINITION + ******************************************************************************/ +#define MOD_NO_IN_1_DEVAPC 16 + +/****************************************************************************** + * Bit Field DEFINITION + ******************************************************************************/ +DEFINE_BIT(SCP_SSPM_SEC, 21) + +#endif diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c index e20b447..3ad83f7 100644 --- a/src/soc/mediatek/mt8186/soc.c +++ b/src/soc/mediatek/mt8186/soc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <soc/devapc.h> #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> @@ -15,6 +16,7 @@ { mtk_mmu_disable_l2c_sram(); sspm_init(); + dapc_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Gerrit-Change-Number: 60317 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Move some definations of devapc to common folder
by Felix Held (Code Review) 28 Dec '21

28 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60394 ) Change subject: soc/mediatek/mt8195: Move some definations of devapc to common folder ...................................................................... soc/mediatek/mt8195: Move some definations of devapc to common folder Move some definations of devapc for sharing between MT8195 and MT8186. BUG=b:202871018 TEST=emerge-cherry coreboot; emerge-corsola coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60394 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/soc/mediatek/common/include/soc/devapc_common.h M src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/devapc.h 4 files changed, 52 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/devapc_common.h b/src/soc/mediatek/common/include/soc/devapc_common.h new file mode 100644 index 0000000..666fc70 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/devapc_common.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_DEVAPC_H +#define SOC_MEDIATEK_COMMON_DEVAPC_H + +#define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, + +#define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) + +#define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, \ + PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, \ + PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) + +#define FORBIDDEN2 FORBIDDEN, FORBIDDEN +#define FORBIDDEN3 FORBIDDEN2, FORBIDDEN +#define FORBIDDEN4 FORBIDDEN3, FORBIDDEN +#define FORBIDDEN5 FORBIDDEN4, FORBIDDEN +#define FORBIDDEN6 FORBIDDEN5, FORBIDDEN +#define FORBIDDEN7 FORBIDDEN6, FORBIDDEN +#define FORBIDDEN10 FORBIDDEN3, FORBIDDEN7 +#define FORBIDDEN11 FORBIDDEN10, FORBIDDEN +#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN +#define FORBIDDEN13 FORBIDDEN12, FORBIDDEN +#define FORBIDDEN14 FORBIDDEN13, FORBIDDEN +#define FORBIDDEN15 FORBIDDEN14, FORBIDDEN + +#define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION +#define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION +#define NO_PROTECTION4 NO_PROTECTION3, NO_PROTECTION + +#endif diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c index 3e86289..3a49e38 100644 --- a/src/soc/mediatek/mt8195/apusys_devapc.c +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <soc/apusys_devapc.h> #include <soc/devapc.h> +#include <soc/devapc_common.h> static const enum domain_id domain_map[] = { DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3, DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7, diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index 1b0de8c..ac3e6db 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <soc/devapc.h> +#include <soc/devapc_common.h> #include <soc/apusys_devapc.h> static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { diff --git a/src/soc/mediatek/mt8195/include/soc/devapc.h b/src/soc/mediatek/mt8195/include/soc/devapc.h index 5267b3b..a355fdf 100644 --- a/src/soc/mediatek/mt8195/include/soc/devapc.h +++ b/src/soc/mediatek/mt8195/include/soc/devapc.h @@ -76,51 +76,6 @@ unsigned char d_permission[4]; }; -#define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3) \ - (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ - (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, - -#define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) \ - DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3) \ - DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) - -#define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ - PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ - PERM_ATTR14, PERM_ATTR15) \ - DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, \ - PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) \ - DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ - PERM_ATTR10, PERM_ATTR11, \ - PERM_ATTR12, PERM_ATTR13, \ - PERM_ATTR14, PERM_ATTR15) - -#define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION -#define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION - -#define FORBIDDEN2 FORBIDDEN, FORBIDDEN -#define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN -#define FORBIDDEN7 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN -#define FORBIDDEN10 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN -#define FORBIDDEN11 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN -#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN -#define FORBIDDEN13 FORBIDDEN12, FORBIDDEN -#define FORBIDDEN14 FORBIDDEN13, FORBIDDEN -#define FORBIDDEN15 FORBIDDEN14, FORBIDDEN - enum devapc_sys_dom_num { DOM_NUM_INFRA_AO_SYS0 = 16, DOM_NUM_INFRA_AO_SYS1 = 4, -- To view, visit https://review.coreboot.org/c/coreboot/+/60394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a Gerrit-Change-Number: 60394 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C
by Felix Held (Code Review) 28 Dec '21

28 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60316 ) Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C ...................................................................... soc/mediatek/mt8186: Adjust usage of SRAM L2C We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before DRAM calibration. When we check cbmem, we found the content of this memory is unreadable. The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM has configured only half of L2/L3 cache as SRAM. Therefore, decrease the size of each SRAM region to fit into the first half of the cache. BUG=b:207725851 TEST=Bootblock log looked good in `cbmem -c` Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60316 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/include/soc/memlayout.ld 1 file changed, 11 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index a1700e6..36078d3 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -34,6 +34,12 @@ /* MT8186 has 64KB SRAM. */ SRAM_END(0x00110000) + /* + * The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM + * has configured only half of L2/L3 cache as SRAM and the rest for cache + * so we can't use them unless if we disable L2C and reconfigure (be aware + * we can't configure whole L3 to SRAM without any cache). + */ SRAM_L2C_START(0x00200000) /* 4K reserved for BOOTROM until BOOTBLOCK is started */ BOOTBLOCK(0x00201000, 60K) @@ -41,11 +47,11 @@ * The needed size can be obtained by: * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz */ - DRAM_INIT_CODE(0x00210000, 240K) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K) - PRERAM_CBFS_CACHE(0x00290000, 48K) - PRERAM_CBMEM_CONSOLE(0x0029C000, 400K) - SRAM_L2C_END(0x00300000) + DRAM_INIT_CODE(0x00210000, 196K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K) + PRERAM_CBFS_CACHE(0x00264000, 48K) + PRERAM_CBMEM_CONSOLE(0x00270000, 64K) + SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) -- To view, visit https://review.coreboot.org/c/coreboot/+/60316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Gerrit-Change-Number: 60316 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021