coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: superio/winbond/w83627hf/acpi: Replace Subtract(a,b,c) with ASL 2.0 s...
by HAOUAS Elyes (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Felix Singer, Felix Held. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60476 ) Change subject: superio/winbond/w83627hf/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd97e662ec4be7092a655bc298dffb6d826bc497 Gerrit-Change-Number: 60476 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 30 Dec 2021 04:00:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Change EN_PP3300_SSD and I2C/DDC signals
by Rory Liu (Code Review) 30 Dec '21

30 Dec '21

Rory Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60530 ) Change subject: mb/google/brya/var/brask: Change EN_PP3300_SSD and I2C/DDC signals ...................................................................... mb/google/brya/var/brask: Change EN_PP3300_SSD and I2C/DDC signals The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14, I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12. BUG=b:206602609 TEST=build pass Signed-off-by: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0 --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/brask/gpio.c 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/60530/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 5ad8e46..e17c751 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -139,10 +139,10 @@ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC(GPP_D12, NONE), + /* D11 : ISH_SPI_MISO ==> DDIA_DP_CTRLCLK */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> DDIA_DP_CTRLDATA */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), /* D13 : ISH_UART0_RXD ==> TP97 */ PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> TP93 */ @@ -202,10 +202,10 @@ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_RX_STRAP */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), - /* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), @@ -235,8 +235,8 @@ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), - /* F14 : GSXDIN ==> NC */ - PAD_NC(GPP_F14, NONE), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ @@ -386,10 +386,10 @@ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index da17230..86a906e 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -26,10 +26,10 @@ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0 Gerrit-Change-Number: 60530 Gerrit-PatchSet: 1 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8186 Corsola review ToT
by Rex-BC Chen (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Rex-BC Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58639 to look at the new patch set (#73). Change subject: DO-NOT-SUBMIT: MT8186 Corsola review ToT ...................................................................... DO-NOT-SUBMIT: MT8186 Corsola review ToT Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58639/73 -- To view, visit https://review.coreboot.org/c/coreboot/+/58639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 Gerrit-Change-Number: 58639 Gerrit-PatchSet: 73 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Increase size of CBFS_MCACHE
by Rex-BC Chen (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60529 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Increase size of CBFS_MCACHE ...................................................................... soc/mediatek/mt8186: Increase size of CBFS_MCACHE The current CBFS mcache size (roughly 7KiB) is insufficient for mt8186, so increase it by 1KiB. Error logs: CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size! CBFS: mcache @0x0010e004 built for 63 files, used 0xde4 of 0xdfc bytes BUG=b:202871018 TEST=no cbfs error logs. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f --- M src/soc/mediatek/mt8186/include/soc/memlayout.ld 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/60529/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f Gerrit-Change-Number: 60529 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: Initialize krabby display
by Rex-BC Chen (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60447 to look at the new patch set (#5). Change subject: mb/google/corsola: Initialize krabby display ...................................................................... mb/google/corsola: Initialize krabby display PS8640 is used on Krabby board as the eDP bridge IC. Enable PS8640 and configure display in mainboard_init() to support display in firmware screen. BUG=b:210806060 TEST=saw firmware display on eDP panel of krabby and kingler. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I314d5407c40429bb7bc50f36fece58e396b27548 --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/display.c M src/mainboard/google/corsola/display.h 3 files changed, 93 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/60447/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/60447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314d5407c40429bb7bc50f36fece58e396b27548 Gerrit-Change-Number: 60447 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Increase size of CBFS_MCACHE
by Rex-BC Chen (Code Review) 30 Dec '21

30 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60529 ) Change subject: soc/mediatek/mt8186: Increase size of CBFS_MCACHE ...................................................................... soc/mediatek/mt8186: Increase size of CBFS_MCACHE The current CBFS mcache size (roughly 7KiB) is insufficient for mt8186, so increase it by 1KiB. Error logs: CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size! CBFS: mcache @0x0010e004 built for 63 files, used 0xde4 of 0xdfc bytes BUG=b:202871018 TEST=no cbfs error logs. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f --- M src/soc/mediatek/mt8186/include/soc/memlayout.ld 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/60529/1 diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index 36078d3..e57e323 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -23,13 +23,13 @@ { SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) - STACK(0x00103000, 8K) - TTB(0x00105000, 28K) - DMA_COHERENT(0x0010C000, 4K) - TPM_TCPA_LOG(0x0010D000, 2K) - FMAP_CACHE(0x0010D800, 2K) - WATCHDOG_TOMBSTONE(0x0010E000, 4) - CBFS_MCACHE(0x0010E004, 7K - 4) + TTB(0x00103000, 28K) + DMA_COHERENT(0x0010A000, 4K) + STACK(0x0010B000, 7K) + TPM_TCPA_LOG(0x0010CC00, 2K) + FMAP_CACHE(0x0010D400, 2K) + WATCHDOG_TOMBSTONE(0x0010DC00, 4) + CBFS_MCACHE(0x0010DC04, 8K - 4) TIMESTAMP(0x0010FC00, 1K) /* MT8186 has 64KB SRAM. */ SRAM_END(0x00110000) -- To view, visit https://review.coreboot.org/c/coreboot/+/60529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f Gerrit-Change-Number: 60529 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Update vboot submodule to upstream master
by Hsuan-ting Chen (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Julius Werner. Hello Hsuan Ting Chen, Edward O'Callaghan, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60078 to look at the new patch set (#3). Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 13f601fb: 2021-09-24 12:25:24 +0000 - (vboot: boot from miniOS recovery kernels on disk) to commit id 25b94935: 2021-12-29 21:34:41 +0000 - (vboot_ref/futility: Wrap flashrom_drv behind USE_FLASHROM) This brings in 44 new commits. Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Change-Id: Ife75d21ddfa0b956fdf7a638cd53b55b11f6cb7d --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/60078/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife75d21ddfa0b956fdf7a638cd53b55b11f6cb7d Gerrit-Change-Number: 60078 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: initialize krabby display
by Rex-BC Chen (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60447 ) Change subject: mb/google/corsola: initialize krabby display ...................................................................... Patch Set 4: (1 comment) Patchset: PS1: > https://review.coreboot. […] it's built pass with CB:60515. @hung-te, is this ok for you? -- To view, visit https://review.coreboot.org/c/coreboot/+/60447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314d5407c40429bb7bc50f36fece58e396b27548 Gerrit-Change-Number: 60447 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 03:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
by Rob Barnes (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Bhanu Prakash Maiya, Kenneth Chan, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60442 ) Change subject: mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60442/comment/86ea3cb6_9d986ac0 PS4, Line 11: 1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2. New id is 10EC1019:1/10EC1019:2 right? So 10EC1019:1/10EC1019:2 from 10EC1019:0/10EC1019:1? File src/mainboard/google/guybrush/variants/dewatt/overridetree.cb: https://review.coreboot.org/c/coreboot/+/60442/comment/e9acd419_4a1f4fd3 PS4, Line 151: register "uid" = "1" "probed" = "1"? -- To view, visit https://review.coreboot.org/c/coreboot/+/60442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542f886fe63205777837d7146169177b043cc5f2 Gerrit-Change-Number: 60442 Gerrit-PatchSet: 4 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 03:33:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting
by Rob Barnes (Code Review) 30 Dec '21

30 Dec '21

Attention is currently required from: Paul Menzel, Kenneth Chan, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60328 ) Change subject: mb/google/guybrush/var/dewatt: disable unused PCIe clock setting ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If449453bc60ed41e104346429babc06a73acef64 Gerrit-Change-Number: 60328 Gerrit-PatchSet: 4 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 30 Dec 2021 03:22:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021