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Change subject: mb/google/brya/var/brask: Change I2C/DDC signals
......................................................................
mb/google/brya/var/brask: Change I2C/DDC signals
The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14,
I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12.
BUG=b:206602609
TEST=build pass
Signed-off-by: Rory Liu <rory.liu(a)quanta.corp-partner.google.com>
Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0
---
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/brask/gpio.c
2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/60530/3
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Change subject: Update vboot submodule to upstream master
......................................................................
Patch Set 4:
(1 comment)
File 3rdparty/vboot:
https://review.coreboot.org/c/coreboot/+/60078/comment/46f2cea8_b0092ddb
PS2, Line 1: 8028cac33c9c408f90de9ceffc714a1a0ca9d583
> 25b9493525325dfb5bc2c36321c43ec7665060fa […]
Done
It is great to hear that CL finally landed!
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Change subject: mb/google/brya/var/brask: Change I2C/DDC signals
......................................................................
Patch Set 2:
(1 comment)
This change is ready for review.
File src/mainboard/google/brya/variants/baseboard/brask/gpio.c:
https://review.coreboot.org/c/coreboot/+/60530/comment/1af71842_d0253e70
PS1, Line 145: PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
> NF2
Ack
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Change subject: mb/google/guybrush/var/dewatt: Update for RT1019 amp dev id was changed
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60442/comment/4386864a_737007b6
PS4, Line 11: 1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2.
> New id is 10EC1019:1/10EC1019:2 right? So 10EC1019:1/10EC1019:2 from 10EC1019:0/10EC1019:1?
Original code is referring to guybrush , using I2C 0x28, 0x29, 0x2a for 1019. 0x28 (1019:0) can't be mapped (dewatt using 0x29, 0x2a), so the 1019 works will with id 1019:1 and 1019:2 before this changed. Now we can remove 0x28 and mapping id to 1019:0 and 1019:1 for audio works well. (It's failed before, w/o 0x28)
File src/mainboard/google/guybrush/variants/dewatt/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/60442/comment/97a7d805_59f12333
PS4, Line 151: register "uid" = "1"
> "probed" = "1"?
I refer to guybrush CRB codes, 0x29 w/o probed=1 and 0x2a with probed=1
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xin hua wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58188 )
Change subject: nb/intel/sandybridge: Populate meminfo when using MRC
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
What is the cause of this?
ft232h log with raminit debug enabled
https://pastebin.com/kHC0bXLs
Read MPR training failed: 1, 2, 0
raminit failed
----
If I remove the patches in here it boots fine
ft232h log with raminit debug enabled
https://pastebin.com/e8xhet1V
Any ideas? Thx
If I need more debugging options please tell me how to enable it, thx
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Change subject: ec/lenovo/h8/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
Why don't you convert the files to ASL 2.0 in one go?
( https://review.coreboot.org/q/topic:ASL_2 )
File src/ec/lenovo/h8/acpi/thermal.asl:
https://review.coreboot.org/c/coreboot/+/60492/comment/946ee138_4dd1181b
PS1, Line 15: Local0 = Local0 + 2732
Local0 += 2732
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Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/google/dedede/variants/magolor/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/60301/comment/79558f00_ca185297
PS9, Line 111: register "CdClock" = "0x0"
> Based on the latest code change in CL#60009, you may need to change the setting to […]
fixed.
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Hello build bot (Jenkins), Henry Sun, Angel Pons, Simon Yang, Kane Chen, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
......................................................................
mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
When using the default initial core display clock frequency, Magolor has
a rare stability issue where the startup of Chrome OS in secure mode may
hang. Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommendation avoids this problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for magolor.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/magolor/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60301/10
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Change subject: sb/intel/bd82x6x/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
......................................................................
Patch Set 1: Code-Review+2
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Change subject: arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
......................................................................
Patch Set 1: Code-Review+2
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