coreboot-gerrit November 2021

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Change in coreboot[master]: security/intel/txt: Get addr bits at runtime
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58684 ) Change subject: security/intel/txt: Get addr bits at runtime ...................................................................... security/intel/txt: Get addr bits at runtime This removes the need for a Kconfig value. Change-Id: Ia9f39aa1c7fb9a64c2e5412bac6e2600b222a635 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58684 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/security/intel/txt/getsec_mtrr_setup.inc M src/security/intel/txt/getsec_sclean.S 2 files changed, 11 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/security/intel/txt/getsec_mtrr_setup.inc b/src/security/intel/txt/getsec_mtrr_setup.inc index 15e8cc1..44471eb 100644 --- a/src/security/intel/txt/getsec_mtrr_setup.inc +++ b/src/security/intel/txt/getsec_mtrr_setup.inc @@ -3,8 +3,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) - /* * Configure the MTRRs to cache the BIOS ACM. No general-purpose * registers are preserved. Inputs are taken from SSE registers: @@ -16,6 +14,16 @@ */ .macro SET_UP_MTRRS_FOR_BIOS_ACM + /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + movl %edx, %edi /* %edi contains the MTRR_HIGH_MASK */ + /* Get the number of variable MTRRs */ movl $(MTRR_CAP_MSR), %ecx rdmsr @@ -56,7 +64,7 @@ movd %eax, %xmm1 /* Program MTRR mask */ - movl MTRR_HIGH_MASK, %edx + movl %edi, %edx xorl %eax, %eax subl %ebx, %eax /* %eax = 4GIB - size to cache */ orl $(MTRR_PHYS_MASK_VALID), %eax diff --git a/src/security/intel/txt/getsec_sclean.S b/src/security/intel/txt/getsec_sclean.S index e240a2f..0944e15 100644 --- a/src/security/intel/txt/getsec_sclean.S +++ b/src/security/intel/txt/getsec_sclean.S @@ -6,8 +6,6 @@ #include "getsec_mtrr_setup.inc" -#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) - #define NO_EVICT_MODE 0x2e0 .align 4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9f39aa1c7fb9a64c2e5412bac6e2600b222a635 Gerrit-Change-Number: 58684 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/storo: Add fw_config probe for multi audio codec
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58643 ) Change subject: mb/google/dedede/var/storo: Add fw_config probe for multi audio codec ...................................................................... mb/google/dedede/var/storo: Add fw_config probe for multi audio codec Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS" BUG=b:202463494 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com> Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 90ad9ad..5fe27a5 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end + chip soc/intel/jasperlake # USB Port Configuration @@ -279,7 +287,23 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end end # I2C 4 device pci 1f.3 on -- To view, visit https://review.coreboot.org/c/coreboot/+/58643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905 Gerrit-Change-Number: 58643 Gerrit-PatchSet: 2 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: yongkun yu <yuyongkun(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brya0: add HPS as generic I2C peripheral
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58646 ) Change subject: mb/google/brya/var/brya0: add HPS as generic I2C peripheral ...................................................................... mb/google/brya/var/brya0: add HPS as generic I2C peripheral Some brya0 units have HPS fitted and connected to PCH I2C2, rather than a user-facing camera. Because HPS uses I2C address 0x51, which may conflict with the user-facing camera EEPROM, introduce a new fw_config bit to indicate whether HPS is present. BUG=b:202784200 TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage TEST=ectool cbi set 6 0x28191 4 # set bit 17 for HPS TEST=flashrom -p internal -w image-brya0.serial.bin Signed-off-by: Dan Callaghan <dcallagh(a)google.com> Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index ad2399b..f3b7925 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -27,6 +27,11 @@ option UFC_USB 0 option UFC_MIPI_IMX208 1 end + # Bits 15 and 16 were intended for WFC but never declared here + field HPS 17 17 + option HPS_ABSENT 0 + option HPS_PRESENT 1 + end end chip soc/intel/alderlake @@ -532,6 +537,19 @@ probe UFC UFC_MIPI_IMX208 end end + chip drivers/i2c/generic + register "hid" = ""GOOG0020"" + register "desc" = ""Chrome OS HPS"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL + # HPS uses I2C addresses 0x30 and 0x51. + # The address we provide here is not significant because + # neither coreboot nor Linux have a driver for HPS, + # it's only used from userspace. + device i2c 30 on + probe HPS HPS_PRESENT + end + end end device ref i2c3 on end device ref i2c5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/58646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e Gerrit-Change-Number: 58646 Gerrit-PatchSet: 4 Gerrit-Owner: Dan Callaghan <dcallagh(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: MAINTAINERS: Add myself as a maintainer for ASUS A88XM-E
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58659 ) Change subject: MAINTAINERS: Add myself as a maintainer for ASUS A88XM-E ...................................................................... MAINTAINERS: Add myself as a maintainer for ASUS A88XM-E I also have this board in addition to G505S and AM1I-A. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0fe3ee6524209980a463b7835128b5c40f5d4ca5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58659 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M MAINTAINERS 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Mike Banon: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index e638ad2..84e855c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -169,6 +169,11 @@ +ASUS A88XM-E MAINBOARD +M: Mike Banon <mikebdp2(a)gmail.com> +S: Maintained +F: src/mainboard/asus/a88xm-e/ + ASUS AM1I-A MAINBOARD M: Mike Banon <mikebdp2(a)gmail.com> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/58659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe3ee6524209980a463b7835128b5c40f5d4ca5 Gerrit-Change-Number: 58659 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: MAINTAINERS: Add myself as a maintainer for ASUS A88XM-E
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58659 ) Change subject: MAINTAINERS: Add myself as a maintainer for ASUS A88XM-E ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe3ee6524209980a463b7835128b5c40f5d4ca5 Gerrit-Change-Number: 58659 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 15:57:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek/mt8195: Remove unused code and comments
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58635 ) Change subject: vc/mediatek/mt8195: Remove unused code and comments ...................................................................... vc/mediatek/mt8195: Remove unused code and comments Remove unused code and comment to align with the latest MTK memory reference code which is from MTK internal dram driver code without upstream. version: Ib59134533ced8de09d23dd9f347c934d315166e2 TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c M src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c M src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c M src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c M src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c M src/vendorcode/mediatek/mt8195/dramc/Hal_io.c M src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c M src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c M src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c M src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c M src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c M src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c M src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c M src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c M src/vendorcode/mediatek/mt8195/dramc/emi.c M src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h M src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h M src/vendorcode/mediatek/mt8195/include/dramc_register.h M src/vendorcode/mediatek/mt8195/include/dramc_top.h M src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h 24 files changed, 5,046 insertions(+), 15,466 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d Gerrit-Change-Number: 58635 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/lpc: Remove the weak function
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58770 ) Change subject: amd/lpc: Remove the weak function ...................................................................... amd/lpc: Remove the weak function BUG=b:140165023 Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58770 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc.c 2 files changed, 0 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index daa51f1..09eafb8 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -141,8 +141,6 @@ /* Clear all decoding to the LPC bus and erase any range registers associated * with the enable bits. */ void lpc_disable_decodes(void); -/* LPC is typically enabled very early, but this function is last opportunity */ -void soc_late_lpc_bridge_enable(void); void lpc_enable_port80(void); void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 365c14dbf..496816b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -20,9 +20,6 @@ #include <soc/lpc.h> #include <soc/southbridge.h> -/* Most systems should have already enabled the bridge */ -void __weak soc_late_lpc_bridge_enable(void) { } - static void setup_serirq(void) { u8 byte; @@ -41,8 +38,6 @@ { u8 byte; - soc_late_lpc_bridge_enable(); - /* Initialize isa dma */ isa_dma_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/58770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Gerrit-Change-Number: 58770 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/cse: Add get_me_fw_version function
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58520 ) Change subject: soc/intel/common/block/cse: Add get_me_fw_version function ...................................................................... soc/intel/common/block/cse: Add get_me_fw_version function Modify print_me_fw_version to get ME firmware version by calling it. Tested=On a not yet to be public platform, verified the function can get ME FW version successfully. Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: I50d472a413bcaaaa085955657bde6a0e6ec2c1db Reviewed-on: https://review.coreboot.org/c/coreboot/+/58520 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 51 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 68a41e8..f37ff95 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -813,42 +813,43 @@ void print_me_fw_version(void *unused) { - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_GEN_GET_FW_VERSION, - }; - - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); + struct me_fw_ver_resp resp = {0}; /* Ignore if UART debugging is disabled */ if (!CONFIG(CONSOLE_SERIAL)) return; + if (get_me_fw_version(&resp) == CB_SUCCESS) { + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + } + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} + +enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) +{ + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_GEN_GET_FW_VERSION, + }; + + if (resp == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", __func__); + return CB_ERR; + } + size_t resp_size = sizeof(*resp); + /* Ignore if CSE is disabled */ if (!is_cse_enabled()) - return; + return CB_ERR; /* * Ignore if ME Firmware SKU type is Lite since * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. */ if (cse_is_hfs3_fw_sku_lite()) - return; + return CB_ERR; /* * Prerequisites: @@ -858,23 +859,19 @@ * during ramstage */ if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) - goto fail; + return CB_ERR; heci_reset(); - if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size, + if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), resp, &resp_size, HECI_MKHI_ADDR)) - goto fail; + return CB_ERR; - if (resp.hdr.result) - goto fail; + if (resp->hdr.result) + return CB_ERR; - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; -fail: - printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); + return CB_SUCCESS; } void cse_trigger_vboot_recovery(enum csme_failure_reason reason) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 80e28d5..7f45570 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -76,6 +76,22 @@ uint16_t build; } __packed; +/* ME FW Version */ +struct me_version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; +} __packed; + +/* ME FW Version response */ +struct me_fw_ver_resp { + struct mkhi_hdr hdr; + struct me_version code; + struct me_version rec; + struct me_version fitc; +} __packed; + /* CSE recovery sub-error codes */ enum csme_failure_reason { /* No error */ @@ -227,6 +243,11 @@ void print_me_fw_version(void *unused); /* + * Queries and gets ME firmware version + */ +enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp); + +/* * Checks current working operation state is normal or not. * Returns true if CSE's current working state is normal, otherwise false. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d472a413bcaaaa085955657bde6a0e6ec2c1db Gerrit-Change-Number: 58520 Gerrit-PatchSet: 10 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelly_Chang(a)wiwynn.com Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib: Add new TS for IA pre-cpu reset entities
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57969 ) Change subject: commonlib: Add new TS for IA pre-cpu reset entities ...................................................................... commonlib: Add new TS for IA pre-cpu reset entities The idea here is to capture the various boot entities prior to IA cpu reset. BUG=b:182575295 TEST=Boot to OS, check cbmem -t output Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: If89befa362d7852a2c0743d05155a0b6c1634672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57969 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 6330b75..98fe552 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -113,6 +113,11 @@ TS_ME_INFORM_DRAM_DONE = 941, TS_ME_BEFORE_END_OF_POST = 942, TS_ME_AFTER_END_OF_POST = 943, + TS_ME_BOOT_STALL_DONE = 944, + TS_ME_ICC_CONFIG_START = 945, + TS_ME_HOST_BOOT_PREP_DONE = 946, + TS_ME_RECEIVED_CRDA_FROM_PMC = 947, + TS_FIT_UCODE_LOADED = 948, /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, @@ -267,6 +272,11 @@ { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, { TS_ME_BEFORE_END_OF_POST, "before sending EOP to ME"}, { TS_ME_AFTER_END_OF_POST, "after sending EOP to ME"}, + { TS_ME_BOOT_STALL_DONE, "CSE sent 'Boot Stall Done' to PMC"}, + { TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"}, + { TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"}, + { TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"}, + { TS_FIT_UCODE_LOADED, "CPU has loaded UCODE/PCODE from FIT"}, /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/57969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If89befa362d7852a2c0743d05155a0b6c1634672 Gerrit-Change-Number: 57969 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for brask
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58729 ) Change subject: mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for brask ...................................................................... mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for brask Enable DRIVERS_GENESYSLOGIC_GL9755 support for brask. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58729 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7f24adb..ed9d82c 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -12,6 +12,7 @@ config BOARD_GOOGLE_BRASK bool "-> Brask" select BOARD_GOOGLE_BASEBOARD_BRASK + select DRIVERS_GENESYSLOGIC_GL9755 select SOC_INTEL_CRASHLOG select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES -- To view, visit https://review.coreboot.org/c/coreboot/+/58729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71 Gerrit-Change-Number: 58729 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021