coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/guybrush: Update STT coefficients
by Jason Glenesk (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Paul Menzel, Matt Papageorge. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58674 ) Change subject: mb/google/guybrush: Update STT coefficients ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58674/comment/7db3d893_5f9f9548 PS2, Line 9: Update guybrush STT (Skin Temperature Tracking) configuration settings. > Where are the values from? The power team provides them after tuning the board. I added that bit in the message. -- To view, visit https://review.coreboot.org/c/coreboot/+/58674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Gerrit-Change-Number: 58674 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 18:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Update STT coefficients
by Jason Glenesk (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Matt Papageorge. Hello build bot (Jenkins), Rob Barnes, Matt Papageorge, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58674 to look at the new patch set (#3). Change subject: mb/google/guybrush: Update STT coefficients ...................................................................... mb/google/guybrush: Update STT coefficients Update guybrush STT (Skin Temperature Tracking) configuration settings to values provided by power team after tuning. BUG=b:203123658 Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58674/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Gerrit-Change-Number: 58674 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56580 to look at the new patch set (#9). Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... commonlib/mem_pool: Allow configuring the alignment AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 --- M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/mem_pool.c M src/lib/cbfs.c 3 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56580/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58707 ) Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/common/block/lpc/Kconfig: https://review.coreboot.org/c/coreboot/+/58707/comment/50890b78_0c8e51af PS4, Line 23: The LPC SPI DMA controller requires the destination buffers to be 64 > Adding `help` text for an override is kinda weird. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Gerrit-Change-Number: 58707 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 18:03:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58707 to look at the new patch set (#5). Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA ...................................................................... soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec --- M src/soc/amd/common/block/lpc/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/58707/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Gerrit-Change-Number: 58707 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Hello build bot (Jenkins), Julius Werner, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58706 to look at the new patch set (#5). Change subject: lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option ...................................................................... lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig option This option will allow platforms to set the alignment of the cbfs_cache buffers. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 8, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 --- M src/lib/Kconfig M src/lib/cbfs.c 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/58706/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Gerrit-Change-Number: 58706 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56580 ) Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... Patch Set 8: (1 comment) File src/commonlib/include/commonlib/mem_pool.h: https://review.coreboot.org/c/coreboot/+/56580/comment/764e830c_11328063 PS7, Line 65: 0 > See Karthik's comment here: https://review.coreboot. […] Done. I just added a parameter and updated the callers. -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 18:03:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56580 to look at the new patch set (#8). Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... commonlib/mem_pool: Allow configuring the alignment AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 --- M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/mem_pool.c M src/lib/cbfs.c 3 files changed, 16 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56580/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/region: Add rdev_readat_full helper method
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58761 ) Change subject: commonlib/region: Add rdev_readat_full helper method ...................................................................... commonlib/region: Add rdev_readat_full helper method This helper method makes the code a bit cleaner. BUG=b:179699789 TEST=none Suggested-by: Julius Werner <jwerner(a)chromium.org> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie442217eba2e8f99de1407d61f965428b5c6f3bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58761 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/commonlib/include/commonlib/region.h 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 764870f..5d73d9e 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -158,6 +158,17 @@ } /* + * Returns < 0 on error otherwise returns size of data read at provided + * offset filling in the buffer passed. + * + * You must ensure the buffer is large enough to hold the full region_device. + */ +static inline ssize_t rdev_readat_full(const struct region_device *rd, void *b) +{ + return rdev_readat(rd, b, 0, region_device_sz(rd)); +} + +/* * Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0 * when child is not within the parent's region. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie442217eba2e8f99de1407d61f965428b5c6f3bf Gerrit-Change-Number: 58761 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [NEEDS_TEST]: mb/acer/g43t-am3: Add Acer Q45T-AM as a variant
by Attila Nemčkov (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Michael Büchler. Attila Nemčkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57764 ) Change subject: [NEEDS_TEST]: mb/acer/g43t-am3: Add Acer Q45T-AM as a variant ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Patch builds and boots on Acer Q45T-AM. Mac-Address (descriptor+gbe region) can be generated with ich9gen and embedded with dd as described here: https://libreboot.org/docs/install/ich9utils.html#ich9gen. The original descriptor.bin and gbe.bin from the stock firmware can also be integrated at compilation instead through coreboot configuration. Both methods have been tested and confirmed to be working. -- To view, visit https://review.coreboot.org/c/coreboot/+/57764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I425852f4bdacf7cb6688a5fb845ac3001373262e Gerrit-Change-Number: 57764 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Attila Nemčkov <hunne(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Comment-Date: Mon, 01 Nov 2021 17:49:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021