coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya: Correct AT24 NVM address size
by Varshit B Pandya (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58769 ) Change subject: mb/google/brya: Correct AT24 NVM address size ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58769/comment/8ce134f6_6086b011 PS1, Line 17: TEST: > TEST= Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Gerrit-Change-Number: 58769 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 13:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Correct AT24 NVM address size
by Varshit B Pandya (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Tim Wawrzynczak. Hello build bot (Jenkins), Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58769 to look at the new patch set (#2). Change subject: mb/google/brya: Correct AT24 NVM address size ...................................................................... mb/google/brya: Correct AT24 NVM address size Currently, the address size field of AT24 NVM is incorrect, and Linux v5.10 kernel logs the message below: at24 i2c-PRP0001:01: Bad "address-width" property: 14 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0D to 0x10. TEST=Boot brya and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58769/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Gerrit-Change-Number: 58769 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build ...
by Nico Huber (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Bill XIE, Patrick Rudolph, Angel Pons, Julius Werner, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Aaron Durbin. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51671 ) Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time ...................................................................... Patch Set 22: Code-Review+2 (1 comment) File src/arch/x86/bootblock.ld: https://review.coreboot.org/c/coreboot/+/51671/comment/7afec30e_40f77f9e PS22, Line 57: _ID_SECTION_END - _ECFW_PTR Do we know what happens when this overflows? i.e. when _ECFW_PTR > _ID_SECTION_END -- To view, visit https://review.coreboot.org/c/coreboot/+/51671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Gerrit-Change-Number: 51671 Gerrit-PatchSet: 22 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 13:28:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: disabled autonomous GPIO power management
by David Wu (Code Review) 01 Nov '21

01 Nov '21

David Wu has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/58682 ) Change subject: mb/google/brya/var/kano: disabled autonomous GPIO power management ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/58682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6783e0df1404c9a353061fb564210aa0d12896e Gerrit-Change-Number: 58682 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "mb/google/brya/var/kano: disabled autonomous GPIO power manag...
by David Wu (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Tim Wawrzynczak, Felix Held. Hello build bot (Jenkins), Tim Wawrzynczak, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58809 to review the following change. Change subject: Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management" ...................................................................... Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management" This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1. Reason for revert: it will break s0ix. Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/58809/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index e650042..899dd36 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -15,17 +15,6 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/58809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada Gerrit-Change-Number: 58809 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: eventlog: Add a log type for Chrome OS diagnostics
by Hsuan-ting Chen (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Hsuan Ting Chen. Hello Hsuan Ting Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58795 to review the following change. Change subject: eventlog: Add a log type for Chrome OS diagnostics ...................................................................... eventlog: Add a log type for Chrome OS diagnostics Add events for Chrome OS diagnostics in eventlog tool: * ELOG_TYPE_CROS_DIAGNOSTICS(0xb6): diagnostics-related events * ELOG_CROS_LAUNCH_DIAGNOSTICS(0x01): sub-type for diagnostics boot These events are not added anywhere currently. They will be added in another separate commit. Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Change-Id: I1b67fdb46f64db33f581cfb5635103c9f5bbb302 --- M src/commonlib/bsd/include/commonlib/bsd/elog.h M util/cbfstool/eventlog.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/58795/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index 7e564fc..29c781b 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -305,6 +305,10 @@ #define ELOG_TYPE_MI_HRPC 0xb4 #define ELOG_TYPE_MI_HR 0xb5 +/* Chrome OS diagnostics-related events */ +#define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6 +#define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01 + struct elog_event_extended_event { uint8_t event_type; uint32_t event_complement; diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index 3ea352e..1fd4113 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -157,6 +157,7 @@ {ELOG_TYPE_CR50_NEED_RESET, "cr50 Reset Required"}, {ELOG_TYPE_EC_DEVICE_EVENT, "EC Device"}, {ELOG_TYPE_EXTENDED_EVENT, "Extended Event"}, + {ELOG_TYPE_CROS_DIAGNOSTICS, "Diagnostics Mode"}, {ELOG_TYPE_EOL, "End of log"}, }; @@ -533,6 +534,11 @@ {0, NULL}, }; + static const struct valstr cros_diagnostics_types[] = { + {ELOG_CROS_LAUNCH_DIAGNOSTICS, "Launch Diagnostics"}, + {0, NULL}, + }; + switch (event->type) { case ELOG_TYPE_LOG_CLEAR: { const uint16_t *bytes = event_get_data(event); @@ -614,6 +620,10 @@ eventlog_printf("0x%X", ext_event->event_complement); break; } + case ELOG_TYPE_CROS_DIAGNOSTICS: { + const uint8_t *type = event_get_data(event); + eventlog_printf("%s", val2str(*type, cros_diagnostics_types)); + } default: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b67fdb46f64db33f581cfb5635103c9f5bbb302 Gerrit-Change-Number: 58795 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Angel Pons (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 43: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/b6b7672f_0ac73964 PS43, Line 420: params->PchPseShellEnabled = config->PseShellEn; > this should be Kconfig, not a devicetree option What's a "PSE shell"? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 43 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 11:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 01 Nov '21

01 Nov '21

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 43: (4 comments) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/fcbd91ee_d37f3ca7 PS2, Line 480: : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseDmaSbInterruptEnable[0] = 0x0; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseLogOutputChannel = 0x3; //Set the log output to PSE UART 2 : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : params->PchPseTimedGpioPinEnable[5] = 1; : params->PchPseTimedGpioPinEnable[6] = 1; : params->PchPseTimedGpioPinAllocation[0] = 0x0; //Set to top 20 TGPIO pins : params->PchPseTimedGpioPinAllocation[1] = 0x0; //Set to top 20 TGPIO pins : : /* : * Set to predefined GPIO Pin Muxing. If the device is disabled, it : * will not be consumed by FSP. : */ : params->PchPseTgpio6PinMux = 0x8B81A203; //GPIO pin mux for GPP_T3 : params->PchPseTgpio7PinMux = 0x8B82A40B; //GPIO pin mux for GPP_T11 : params->PchPseTgpio8PinMux = 0x8B80A607; //GPIO pin mux for GPP_B7 : params->PchPseTgpio9PinMux = 0x8B80A808; //GPIO pin mux for GPP_B8 : params->PchPseTgpio10PinMux = 0x8B86AA07; //GPIO pin mux for GPP_U7 : params->PchPseTgpio11PinMux = 0x8B86AC0B; //GPIO pin mux for GPP_U11 : params->PchPseTgpio12PinMux = 0x8B86AE13; //GPIO pin mux for GPP_U19 : params->PchPseTgpio13PinMux = 0x8B85B00C; //GPIO pin mux for GPP_D12 : params->PchPseTgpio14PinMux = 0x8B90B214; //GPIO pin mux for GPP_E20 : params->PchPseTgpio15PinMux = 0x8B90B403; //GPIO pin mux for GPP_E3 : params->PchPseTgpio16PinMux = 0x8B90B607; //GPIO pin mux for GPP_E7 : params->PchPseTgpio17PinMux = 0x8B90B80F; //GPIO pin mux for GPP_E15 : params->PchPseTgpio18PinMux = 0x8B90BA06; //GPIO pin mux for GPP_E6 : params->PchPseTgpio19PinMux = 0x8B8DBC01; //GPIO pin mux for GPP_C1 : params->PchPsePwmPinMux[8] = 0x7B706604; //GPIO pin mux for GPP_E4 : params->PchPsePwmPinMux[9] = 0x7B706805; //GPIO pin mux for GPP_E5 : params->PchPsePwmPinMux[10] = 0x7B706A06; //GPIO pin mux for GPP_E6 : params->PchPsePwmPinMux[11] = 0x7B706C11; //GPIO pin mux for GPP_E17 : params->PchPsePwmPinMux[12] = 0x7B706E12; //GPIO pin mux for GPP_E18 : params->PchPsePwmPinMux[13] = 0x7B707013; //GPIO pin mux for GPP_E19 : params->PchPsePwmPinMux[14] = 0x4B64720A; //GPIO pin mux for GPP_H10 : params->PchPsePwmPinMux[15] = 0x4B64740B; //GPIO pin mux for GPP_H11 : params->PchPseSpiMosiPinMux[1] = 0x4B852003; //GPIO pin mux for GPP_D3 : params->PchPseSpiMisoPinMux[1] = 0x4B853002; //GPIO pin mux for GPP_D2 : params->PchPseSpiClkPinMux[1] = 0x4B854001; //GPIO pin mux for GPP_D1 : params->PchPseSpiCs0PinMux[1] = 0x4B855000; //GPIO pin mux for GPP_D0 : params->PchPseI2sTxPinMux[0] = 0x1B702610; //GPIO pin mux for GPP_E16 : params->PchPseI2sRxPinMux[0] = 0x1B70160F; //GPIO pin mux for GPP_E15 : params->PchPseI2sSfrmPinMux[0] = 0x1B704614; //GPIO pin mux for GPP_E21 : params->PchPseI2sSclkPinMux[0] = 0x1B703615; //GPIO pin mux for GPP_E20 > Unfortunately EHL doesnt have this GpioOverride UPD. […] What about requesting GpioOverride from the FSP team? File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/4480d0af_959e1772 PS43, Line 420: params->PchPseShellEnabled = config->PseShellEn; this should be Kconfig, not a devicetree option https://review.coreboot.org/c/coreboot/+/55367/comment/0494f9e4_395ab6e6 PS43, Line 435: params->PchPseTimedGpioPinEnable[5] = 1; : params->PchPseTimedGpioPinEnable[6] = 1; : params->PchPseTgpio6PinMux = 0x8B81A203; : /* Set to top 20 TGPIO pins for Timed GPIO group 0 & 1 */ : params->PchPseTimedGpioPinAllocation[0] = 0x0; //Set to top 20 TGPIO pins : params->PchPseTimedGpioPinAllocation[1] = 0x0; //Set to top 20 TGPIO pins : board-specific? https://review.coreboot.org/c/coreboot/+/55367/comment/54ced434_a17840f9 PS43, Line 427: /* Set the ownership of these devices to PSE */ : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : /* Enable Timed GPIO pin 5 and 6 */ : params->PchPseTimedGpioPinEnable[5] = 1; : params->PchPseTimedGpioPinEnable[6] = 1; : params->PchPseTgpio6PinMux = 0x8B81A203; : /* Set to top 20 TGPIO pins for Timed GPIO group 0 & 1 */ : params->PchPseTimedGpioPinAllocation[0] = 0x0; //Set to top 20 TGPIO pins : params->PchPseTimedGpioPinAllocation[1] = 0x0; //Set to top 20 TGPIO pins : /* Disable PSE DMA Sideband Interrupt for DMA 0 */ : params->PchPseDmaSbInterruptEnable[0] = 0x0; : /* Set the log output to PSE UART 2 */ : params->PchPseLogOutputChannel = 0x3; //Set the log output to PSE UART 2 : isn't that board-specific? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 43 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 10:57:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases/4.15: Fix typo
by Angel Pons (Code Review) 01 Nov '21

01 Nov '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58775 ) Change subject: Documentation/releases/4.15: Fix typo ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e64793c58f2acfbfc42e46782d68bec97088601 Gerrit-Change-Number: 58775 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 10:42:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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