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Change subject: soc/intel/elkhartlake: Introduce Intel PSE
......................................................................
Patch Set 43:
(1 comment)
Patchset:
PS43:
To me it seems that PSE is optional. Comments in reference code claim that PSE can be either fused disabled or set disabled by "Policy" (= UPD). There is a UPD `PchPseEnable` that defaults to 1, leading to the described reset loop, without providing PSE firmware like done in this change.
That means: PchPseEnable should be set and probably a Kconfig should be added, just like for FSP. This way, enabling PSE and providing a blob can be optional.
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Change subject: lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> Looks OK from AMD
Thanks Rob for review
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Change subject: lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
Patchset:
PS8:
Looks OK from AMD
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Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58640/comment/bc6ec4a7_6abcefab
PS2, Line 10:
> And that is big problem, and has to be improved. The commit you referenced should have had a more elaborate commit message.
Then can you find a really good example that is providing all information asked here?
Even the Intel one is probably not good enough: https://review.coreboot.org/c/coreboot/+/44857
Although, they do have a good example of having data sheet name and chapter in the file comments. @Rex can you follow the comment style in CL:44875 and update the files?
/*
* This file is created based on XXX Datasheet
* Document number: 621483
* Chapter number: 2, 3, 4, 27, 28
*/
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Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58640/comment/6853e634_6a3e9fe4
PS2, Line 10:
> Rex, could you add a short paragraph explaining the similarities and differences between mt8186 and […]
Done
File src/soc/mediatek/mt8186/include/soc/timer.h:
https://review.coreboot.org/c/coreboot/+/58640/comment/cb5c7d4d_98071ff2
PS3, Line 9: TIE_0_EN = 1 << 3,
: COMP_15_EN = 1 << 10,
: COMP_20_EN = 1 << 11,
: COMP_25_EN = 1 << 12,
> Rex, if these constants are always the same for platforms using v2 timer, please move them into time […]
I think I would move these to v2 on upcoming patches.
This is just a init patch.
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Change subject: soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC
......................................................................
Patch Set 4: Code-Review+1
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58639
to look at the new patch set (#6).
Change subject: DO-NOT-SUBMIT: MT8186 Corsola review ToT
......................................................................
DO-NOT-SUBMIT: MT8186 Corsola review ToT
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3
---
M README.md
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58639/6
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