coreboot-gerrit November 2021

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Change in coreboot[master]: buildgcc: Remove GDB from crossgcc
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Martin Roth, Stefan Reinauer. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58380 ) Change subject: buildgcc: Remove GDB from crossgcc ...................................................................... Patch Set 1: (1 comment) File util/crossgcc/Makefile: https://review.coreboot.org/c/coreboot/+/58380/comment/052152cb_0826c86b PS1, Line 71: build_gcc build_iasl build_clang all \ : build-i386 build-x64 build-arm \ : build-aarch64 build-riscv build-ppc64 build-nds32le build-nasm \ : clean distclean clean_tempfiles > nit: realign See CB:58796 -- To view, visit https://review.coreboot.org/c/coreboot/+/58380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib56ae0fdc1a50d24ff44c7879c43f8e94a5bfa95 Gerrit-Change-Number: 58380 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 16:26:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc/Makefile: Clean up .PHONY definitions
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58796 ) Change subject: util/crossgcc/Makefile: Clean up .PHONY definitions ...................................................................... util/crossgcc/Makefile: Clean up .PHONY definitions Order functionally: * first "all" and build-$tools * followed by clean * followed by the architecture targets The order was chosen this way because the architecture targets are the mostly likely to continue to grow. While at it, also fix the build_nasm mention (it was build-nasm) and add build_make. Change-Id: Id58338a512d44111b41503d4c14c08be50d51cde Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/Makefile 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58796/1 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 34fb244..288861b 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -68,8 +68,9 @@ distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_clang all \ - build-i386 build-x64 build-arm \ - build-aarch64 build-riscv build-ppc64 build-nds32le build-nasm \ - clean distclean clean_tempfiles +.PHONY: all build_gcc build_iasl build_clang build_make build_nasm \ + clean distclean clean_tempfiles \ + build-i386 build-x64 build-arm build-aarch64 \ + build-riscv build-ppc64 build-nds32le + .NOTPARALLEL: -- To view, visit https://review.coreboot.org/c/coreboot/+/58796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id58338a512d44111b41503d4c14c08be50d51cde Gerrit-Change-Number: 58796 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/cpu: Add support for cbfs_cache region
by Karthik Ramasubramanian (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56578 ) Change subject: soc/amd/common/block/cpu: Add support for cbfs_cache region ...................................................................... Patch Set 9: Code-Review+2 (1 comment) File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld: https://review.coreboot.org/c/coreboot/+/56578/comment/131c82e6_c590cf11 PS9, Line 26: * reserved_dram_end +--------------------------------+ Nit: Can we update the layout picture here? -- To view, visit https://review.coreboot.org/c/coreboot/+/56578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Gerrit-Change-Number: 56578 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 16:17:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Don't send CSE EOP if CSME is disabled
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57149 ) Change subject: soc/intel: Don't send CSE EOP if CSME is disabled ...................................................................... soc/intel: Don't send CSE EOP if CSME is disabled CSE EOP will fail if the CSE is disabled (CB:52800) Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57149 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index e47eb51..4e1c563 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -18,6 +18,7 @@ CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED, CSE_EOP_RESULT_SUCCESS, CSE_EOP_RESULT_ERROR, + CSE_EOP_RESULT_DISABLED, }; static bool cse_disable_mei_bus(void) @@ -100,6 +101,14 @@ * 2) HFSTS1 COM is Normal * 3) Only sent after DID (accomplished by compiling this into ramstage) */ + + if (cse_is_hfs1_com_soft_temp_disable()) { + printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + return CSE_EOP_RESULT_ERROR; + return CSE_EOP_RESULT_DISABLED; + } + if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); return CSE_EOP_RESULT_ERROR; @@ -158,6 +167,9 @@ case CSE_EOP_RESULT_SUCCESS: printk(BIOS_INFO, "CSE EOP successful, continuing boot\n"); break; + case CSE_EOP_RESULT_DISABLED: + printk(BIOS_INFO, "CSE is disabled, continuing boot\n"); + break; case CSE_EOP_RESULT_ERROR: /* fallthrough */ default: printk(BIOS_ERR, "ERROR: Failed to send EOP to CSE, %d\n", result); 19 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/57149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Gerrit-Change-Number: 57149 Gerrit-PatchSet: 22 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: broadwell boards: Do not set `ddr_refresh_2x` again
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Nico Huber, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55810 ) Change subject: broadwell boards: Do not set `ddr_refresh_2x` again ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/auron/variants/buddy/spd/spd.c: https://review.coreboot.org/c/coreboot/+/55810/comment/5d64e447_1a2b1642 PS9, Line 13: pei_data->ddr_refresh_2x = 1; ddr_refresh_2x is a rowhammer mitigation. We had some complications with updating stuff in the field: I think back then, romstage was part of the RO partition and so there had been workarounds (e.g. boot, set the flag, force a resume cycle to reinit RAM into 2x refresh). Could these assignments be related to that? If so, I'd rather keep them, but amend with a comment that it's for old-RO/new-RW scenarios to ensure that refresh_2x is _really_ used under all circumstances. -- To view, visit https://review.coreboot.org/c/coreboot/+/55810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76478689b3aa27c369a0413d9fbde03674d5e528 Gerrit-Change-Number: 55810 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 16:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Add console deinit API, use in SMM handler
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Nico Huber, Johnny Lin, Paul Menzel, Rocky Phagura, Christian Walter, Angel Pons, Arthur Heymans, Kyösti Mälkki, Peter Tsung Ho Wu, Deomid "rojer" Ryabkov, Ron Minnich. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56386 ) Change subject: Add console deinit API, use in SMM handler ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56386/comment/db42f4c1_d96d8e69 PS11, Line 14: on an OCP Delta Lake server: uart8250_init disables interrupts because it uart8250_init should only be called in the first SMM call (that prints something), no? That's normally early enough to be still within coreboot. What's going on here? -- To view, visit https://review.coreboot.org/c/coreboot/+/56386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5e51f385f83cb998c244ca1d1ffc10339d3a714 Gerrit-Change-Number: 56386 Gerrit-PatchSet: 11 Gerrit-Owner: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Attention: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 16:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Bao Zheng, Marshall Dawson, Zheng Bao, Matt Papageorge, Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58555 ) Change subject: amdfwtool: Set soc name for Stoneyridge ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/58555/comment/03c86950_68d2bbd3 PS3, Line 1588: retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, Is efs not supported with stoneyridge (and so this behavior is as it should be) or is this just a precaution to keep the behavior the same even though you added a --soc argument to the command? -- To view, visit https://review.coreboot.org/c/coreboot/+/58555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Gerrit-Change-Number: 58555 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 16:05:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: Set GNVS DPTE via devicetree
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57988 ) Change subject: soc/intel/braswell: Set GNVS DPTE via devicetree ...................................................................... soc/intel/braswell: Set GNVS DPTE via devicetree Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/facebook/fbg1701/acpi_tables.c M src/mainboard/google/cyan/acpi_tables.c M src/mainboard/google/cyan/devicetree.cb M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/strago/devicetree.cb M src/mainboard/portwell/m107/acpi_tables.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/chip.h 8 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Frans Hendriks: Looks good to me, approved diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index 226da41..3576455 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -15,9 +15,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* Disable DPTF */ - gnvs->dpte = 0; - /* PMIC is configured in I2C1, hide it for the OS */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0; diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index 42380d5..a8e030a 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -15,9 +15,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* Enable DPTF */ - gnvs->dpte = 1; - /* Disable PMIC I2C port for ACPI for all boards except cyan */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); if (!CONFIG(BOARD_GOOGLE_CYAN)) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index cec1682..c968dfc 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -77,6 +77,8 @@ # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + register "dptf_enable" = "true" + # Enable LPSS and LPE devices in ACPI mode register "lpss_acpi_mode" = "1" register "emmc_acpi_mode" = "0" diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index c47e582..279a5c1 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -15,9 +15,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* Enable DPTF */ - gnvs->dpte = 1; - /* PMIC is configured in I2C1, hidden it from OS */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0; diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 77b07d2..848b0c31 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -66,6 +66,8 @@ # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + register "dptf_enable" = "true" + # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" register "emmc_acpi_mode" = "1" diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index 226da41..3576455 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -15,9 +15,6 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* Disable DPTF */ - gnvs->dpte = 0; - /* PMIC is configured in I2C1, hide it for the OS */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 85e70276..cb9cb2d 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -26,6 +26,8 @@ #include <types.h> #include <wrdd.h> +#include "chip.h" + #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -68,6 +70,10 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { + const struct soc_intel_braswell_config *config = config_of_soc(); + + gnvs->dpte = config->dptf_enable; + /* Fill in the Wi-Fi Region ID */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) gnvs->cid1 = wifi_regulatory_domain(); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index d493ad1..53627be 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -42,6 +42,8 @@ struct soc_intel_braswell_config { bool enable_xdp_tap; + bool dptf_enable; + enum serirq_mode serirq_mode; /* Disable SLP_X stretching after SUS power well loss */ -- To view, visit https://review.coreboot.org/c/coreboot/+/57988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Gerrit-Change-Number: 57988 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/braswell: Set GNVS DPTE via devicetree
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Sumeet R Pawnikar, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, Wim Vervoorn. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57988 ) Change subject: soc/intel/braswell: Set GNVS DPTE via devicetree ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57988/comment/b0ce3363_4c15f0f1 PS1, Line 10: field, as newer Intel platforms do. > I'm afraid I don't have any device to test this with. Matt DeVillier reports: tested on google/edgar (cyan variant), Win 10 still reports DPTF in use -- To view, visit https://review.coreboot.org/c/coreboot/+/57988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Gerrit-Change-Number: 57988 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 16:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell/chip.h: Use `bool` type
by Patrick Georgi (Code Review) 01 Nov '21

01 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57987 ) Change subject: soc/intel/braswell/chip.h: Use `bool` type ...................................................................... soc/intel/braswell/chip.h: Use `bool` type Use `bool` type where applicable. Change-Id: I4d5422c16381676738b8614e8e50737b59739921 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57987 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/chip.h 1 file changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Frans Hendriks: Looks good to me, approved diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 732d73b..d493ad1 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -8,11 +8,11 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include <stdint.h> #include <drivers/intel/gma/i915.h> #include <fsp/util.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> +#include <types.h> #define SVID_CONFIG1 1 #define SVID_CONFIG3 3 @@ -40,12 +40,12 @@ }; struct soc_intel_braswell_config { - uint8_t enable_xdp_tap; + bool enable_xdp_tap; enum serirq_mode serirq_mode; /* Disable SLP_X stretching after SUS power well loss */ - int disable_slp_x_stretch_sus_fail; + bool disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration */ enum lpe_clk_src lpe_codec_clk_src; /* Both are 19.2MHz */ @@ -55,13 +55,13 @@ uint32_t sdcard_cap_high; /* Enable devices in ACPI mode */ - int lpss_acpi_mode; - int emmc_acpi_mode; - int sd_acpi_mode; - int lpe_acpi_mode; + bool lpss_acpi_mode; + bool emmc_acpi_mode; + bool sd_acpi_mode; + bool lpe_acpi_mode; /* Allow PCIe devices to wake system from suspend */ - int pcie_wake_enable; + bool pcie_wake_enable; /* Program USB2_COMPBG register. * [10:7] - select vref to AFE port -- To view, visit https://review.coreboot.org/c/coreboot/+/57987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d5422c16381676738b8614e8e50737b59739921 Gerrit-Change-Number: 57987 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021