coreboot-gerrit November 2021

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Change in coreboot[master]: mb/system76/gaze16: Add System76 Gazelle 16
by Tim Crawford (Code Review) 01 Nov '21

01 Nov '21

Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56956 to look at the new patch set (#15). Change subject: mb/system76/gaze16: Add System76 Gazelle 16 ...................................................................... mb/system76/gaze16: Add System76 Gazelle 16 https://tech-docs.system76.com/models/gaze16/README.html The gaze16 comes in 3 variants due to differences in the discrete GPU and network controller used. - NVIDIA RTX 3050, using Realtek Ethernet controller - NVIDIA RTX 3060, using Realtek Ethernet controller - NVIDIA RTX 3060, using onboard Intel I219-V Ethernet controller Tested on the 3050 variant. Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - 2.5" SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio* - 3.5mm microphone input* - S3 suspend/resume - Booting to Pop!_OS Linux 21.04 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics - Mini DisplayPort output (requires NVIDIA GPU) - 3.5mm audio input/output detection on Windows Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/gaze16.md A src/mainboard/system76/gaze16/Kconfig A src/mainboard/system76/gaze16/Kconfig.name A src/mainboard/system76/gaze16/Makefile.inc A src/mainboard/system76/gaze16/acpi/mainboard.asl A src/mainboard/system76/gaze16/acpi/sleep.asl A src/mainboard/system76/gaze16/board_info.txt A src/mainboard/system76/gaze16/bootblock.c A src/mainboard/system76/gaze16/cmos.default A src/mainboard/system76/gaze16/cmos.layout A src/mainboard/system76/gaze16/devicetree.cb A src/mainboard/system76/gaze16/dsdt.asl A src/mainboard/system76/gaze16/ramstage.c A src/mainboard/system76/gaze16/romstage.c A src/mainboard/system76/gaze16/variant.h A src/mainboard/system76/gaze16/variants/3050/data.vbt A src/mainboard/system76/gaze16/variants/3050/hda_verb.c A src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h A src/mainboard/system76/gaze16/variants/3050/overridetree.cb A src/mainboard/system76/gaze16/variants/3050/ramstage.c A src/mainboard/system76/gaze16/variants/3050/romstage.c A src/mainboard/system76/gaze16/variants/3060/data.vbt A src/mainboard/system76/gaze16/variants/3060/hda_verb.c A src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h A src/mainboard/system76/gaze16/variants/3060/overridetree.cb A src/mainboard/system76/gaze16/variants/3060/ramstage.c A src/mainboard/system76/gaze16/variants/3060/romstage.c 28 files changed, 1,365 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/56956/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/56956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c Gerrit-Change-Number: 56956 Gerrit-PatchSet: 15 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries
by Tim Wawrzynczak (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Nico Huber, Martin Roth, Furquan Shaikh, Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57370 ) Change subject: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries ...................................................................... Patch Set 6: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/57370/comment/fc86ec2c_728bf75a PS6, Line 1186: = {} nit: is this necessary? a static should still get zeroed out? -- To view, visit https://review.coreboot.org/c/coreboot/+/57370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Gerrit-Change-Number: 57370 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:46:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs
by Jason Glenesk (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58696 ) Change subject: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Gerrit-Change-Number: 58696 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:45:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries
by Tim Wawrzynczak (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Nico Huber, Martin Roth, Furquan Shaikh, Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57370 ) Change subject: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57370/comment/ae8bb045_a2869cf1 PS4, Line 35: Although the preprocessor usage isn't particularly elegant, adjusting : the devicetree syntax and/or grammar depending on a Kconfig option is : probably even worse. > A linked list of properties, similar to the linked list of PCIe capabilities? Sounds good. Agreed they are necessary with things as they stand right now, it's just not a great solution. A linked-list is a neat idea, would love to see what you have up your sleeves 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/57370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Gerrit-Change-Number: 57370 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:44:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/i2c: Remove the weak function
by Jason Glenesk (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Bao Zheng, Raul Rangel, Marshall Dawson, Zheng Bao. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58771 ) Change subject: amd/i2c: Remove the weak function ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Are you planning to permanently delete vs. comment out after you prove all the builds work? -- To view, visit https://review.coreboot.org/c/coreboot/+/58771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Gerrit-Change-Number: 58771 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Mon, 01 Nov 2021 19:44:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: DO NOT SUBMIT: Proposed libpayload changes for PCI mmio ops support
by build bot (Jenkins) (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Shelley Chen, Furquan Shaikh, Prasad Malisetty. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58683 ) Change subject: DO NOT SUBMIT: Proposed libpayload changes for PCI mmio ops support ...................................................................... Patch Set 3: (4 comments) File payloads/libpayload/drivers/pci_ops.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131914): https://review.coreboot.org/c/coreboot/+/58683/comment/6ab7d72c_d150bb58 PS3, Line 31: pcidev_t * dev) "foo * bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131914): https://review.coreboot.org/c/coreboot/+/58683/comment/bf5739b6_598f3440 PS3, Line 75: int pci_find_device(u16 vid, u16 did, pcidev_t * dev) "foo * bar" should be "foo *bar" File src/lib/coreboot_table.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131914): https://review.coreboot.org/c/coreboot/+/58683/comment/979929c4_d8a76405 PS3, Line 502: (CONFIG_MMIO_LENGTH > 0)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131914): https://review.coreboot.org/c/coreboot/+/58683/comment/5b2a13ee_4f0197d1 PS3, Line 502: (CONFIG_MMIO_LENGTH > 0)) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/58683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2799b35fb0c348896c078ff5356052fc85e05eb Gerrit-Change-Number: 58683 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:44:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: DO NOT SUBMIT: Proposed libpayload changes for PCI mmio ops support
by Shelley Chen (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Shelley Chen, Furquan Shaikh, Prasad Malisetty. Hello build bot (Jenkins), Furquan Shaikh, Prasad Malisetty, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58683 to look at the new patch set (#3). Change subject: DO NOT SUBMIT: Proposed libpayload changes for PCI mmio ops support ...................................................................... DO NOT SUBMIT: Proposed libpayload changes for PCI mmio ops support Proposal for changes to reoriganize the code submitted by Qualcomm for CB:57614 and CB:57615. The idea is to have every platform define their own get_pci_mmio_cfgbase() function when needed and reuse the rest of the code defined in pci_mmio_ops.c. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B Signed-off-by: Shelley Chen <shchen(a)google.com> Change-Id: Ic2799b35fb0c348896c078ff5356052fc85e05eb --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc C payloads/libpayload/drivers/pci_io_ops.c R payloads/libpayload/drivers/pci_mmio_ops.c M payloads/libpayload/drivers/pci_ops.c A payloads/libpayload/drivers/qc_pci_mmio_ops.c M src/device/Kconfig M src/lib/coreboot_table.c M src/soc/qualcomm/sc7280/Kconfig 10 files changed, 125 insertions(+), 180 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/58683/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2799b35fb0c348896c078ff5356052fc85e05eb Gerrit-Change-Number: 58683 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Extract out-of-bounds check to a function and move
by Jason Glenesk (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58764 ) Change subject: amdfwtool: Extract out-of-bounds check to a function and move ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Gerrit-Change-Number: 58764 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:41:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Change the definition of level to a bitwise form
by Jason Glenesk (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58765 ) Change subject: amdfwtool: Change the definition of level to a bitwise form ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Gerrit-Change-Number: 58765 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Nov 2021 19:39:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
by Raul Rangel (Code Review) 01 Nov '21

01 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58707 to look at the new patch set (#7). Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA ...................................................................... soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec --- M src/soc/amd/common/block/lpc/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/58707/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Gerrit-Change-Number: 58707 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021