coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: drivers/ipmi: Fix type mismatch in print statements
by Paul Menzel (Code Review) 09 Nov '21

09 Nov '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59055 ) Change subject: drivers/ipmi: Fix type mismatch in print statements ...................................................................... drivers/ipmi: Fix type mismatch in print statements The size of char * differs between 32-bit and 64-bit. Fix the mismatches in `read_fru_chassis_info_area()`. CC ramstage/drivers/ipmi/ipmi_fru.o src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_chassis_info_area': src/drivers/ipmi/ipmi_fru.c:192:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 192 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 193 | "chassis custom data array.\n", __func__, 194 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_board_info_area': src/drivers/ipmi/ipmi_fru.c:291:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 291 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 292 | "board custom data array.\n", __func__, 293 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_product_info_area': src/drivers/ipmi/ipmi_fru.c:398:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=] 398 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for " | ~~^ | | | long int | %d 399 | "product custom data array.\n", __func__, 400 | info->custom_count * sizeof(char *)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | unsigned int Change-Id: If0c4266b19d56fa88abc397f305154d473ae1a93 Found-by: gcc (Debian 11.2.0-10) 11.2.0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/ipmi/ipmi_fru.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/59055/1 diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 31ac6c0..9c4ad41 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -189,7 +189,7 @@ info->chassis_custom = malloc(info->custom_count * sizeof(char *)); if (!info->chassis_custom) { - printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + printk(BIOS_ERR, "%s failed to malloc %d bytes for " "chassis custom data array.\n", __func__, info->custom_count * sizeof(char *)); ret = CB_ERR; @@ -288,7 +288,7 @@ info->board_custom = malloc(info->custom_count * sizeof(char *)); if (!info->board_custom) { - printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + printk(BIOS_ERR, "%s failed to malloc %d bytes for " "board custom data array.\n", __func__, info->custom_count * sizeof(char *)); ret = CB_ERR; @@ -395,7 +395,7 @@ info->product_custom = malloc(info->custom_count * sizeof(char *)); if (!info->product_custom) { - printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + printk(BIOS_ERR, "%s failed to malloc %d bytes for " "product custom data array.\n", __func__, info->custom_count * sizeof(char *)); ret = CB_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/59055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c4266b19d56fa88abc397f305154d473ae1a93 Gerrit-Change-Number: 59055 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Fix size_t type mismatch in print statement
by Paul Menzel (Code Review) 09 Nov '21

09 Nov '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59054 ) Change subject: soc/intel/xeon_sp: Fix size_t type mismatch in print statement ...................................................................... soc/intel/xeon_sp: Fix size_t type mismatch in print statement The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC romstage/soc/intel/xeon_sp/memmap.o src/soc/intel/xeon_sp/memmap.c: In function 'fill_postcar_frame': src/soc/intel/xeon_sp/memmap.c:39:62: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 39 | printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size); | ~~^ ~~~~~~~~~~ | | | | long unsigned int size_t {aka unsigned int} | %x As `cbmem_size` is of type `size_t` use the length modifier `z` to match all types on all architectures. Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5 Found-by: gcc (Debian 11.2.0-10) 11.2.0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/xeon_sp/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59054/1 diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 0af0ad2..b640c2d 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -36,7 +36,7 @@ /* Try account for the CBMEM region currently used and for future use */ cbmem_get_region((void **)&cbmem_base, &cbmem_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size); + printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%zx\n", cbmem_base, cbmem_size); /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */ cbmem_base -= 4 * MiB; cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/59054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5 Gerrit-Change-Number: 59054 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Tim Wawrzynczak (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Paul Menzel, Nick Vaccaro, Julius Werner, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58253 ) Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/mainboard/google/mistral/chromeos.c: https://review.coreboot.org/c/coreboot/+/58253/comment/5c88cda7_9bd10396 PS5, Line 4: <vendorcode/google/chromeos/chromeos.h> `bootmode.h` -- To view, visit https://review.coreboot.org/c/coreboot/+/58253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Gerrit-Change-Number: 58253 Gerrit-PatchSet: 5 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 20:46:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Karthik Ramasubramanian (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Henry Sun, Frank Chu, Zhuohao Lee. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 8 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 20:36:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
by Karthik Ramasubramanian (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Kevin Chiu, Raul Rangel, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59053 ) Change subject: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/guybrush/variants/guybrush/gpio.c: https://review.coreboot.org/c/coreboot/+/59053/comment/086825d1_4b78028c PS2, Line 57: /* This table is used by guybrush variant with board version >= 2. */ : static const struct soc_amd_gpio bid2_pcie_gpio_table[] = { : }; : Nit: Empty table can be removed and NULL can be returned for bid >= 2. File src/mainboard/google/guybrush/variants/nipperkin/gpio.c: https://review.coreboot.org/c/coreboot/+/59053/comment/c0f26e23_affb9d6e PS2, Line 51: PAD_NC(GPIO_69), Can be removed as well and then bid1_override_pcie_gpio_table can be consolidated with bid2_override_pcie_gpio_table. -- To view, visit https://review.coreboot.org/c/coreboot/+/59053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Gerrit-Change-Number: 59053 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 20:29:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: add list of gpios to lock
by Nick Vaccaro (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58353 ) Change subject: mb/google/brya: add list of gpios to lock ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/gpio.c: https://review.coreboot.org/c/coreboot/+/58353/comment/e57a9329_8845667d PS1, Line 460: SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS > I just saw the comment from Tim in the other CL. Will remove this guarding. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d Gerrit-Change-Number: 58353 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Nov 2021 20:28:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: enable gpio locking
by Nick Vaccaro (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58352 ) Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/alderlake/gpio.c: https://review.coreboot.org/c/coreboot/+/58352/comment/d3f3065c_909db58c PS1, Line 251: #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) > The way it works now, either the MB or the SoC can define the Kconfig without requiring the other on […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 20:27:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: enable gpio locking
by Nick Vaccaro (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58352 ) Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/gpio.c: https://review.coreboot.org/c/coreboot/+/58352/comment/aabed997_666ec49c PS4, Line 278: { GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */ > another pad to consider (for a different reason) is GPP_H3. […] This comment was in a resovled state for some reason, so I didn't catch it until now. I've added GPP_H3. Good catch. -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 7 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 20:26:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: enable gpio locking
by Nick Vaccaro (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58352 to look at the new patch set (#8). Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... soc/intel/alderlake: enable gpio locking This change supplies a list of ADL gpios that are connected to non-host (x86) controllers and should be locked after initial configuration. Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking. BUG=b:210430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/gpio.c 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/58352/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Enable Intel FIVR RFI settings
by Felix Held (Code Review) 09 Nov '21

09 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58878 ) Change subject: soc/intel/alderlake: Enable Intel FIVR RFI settings ...................................................................... soc/intel/alderlake: Enable Intel FIVR RFI settings Add RFI UPD settings to mitigate RFI noise issues and exporting these UPDs to override via board devicetree. BUG=b:200886627 TEST=build Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58878 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 699626b..d259442 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -135,6 +135,22 @@ | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, }; +/* + * FivrSpreadSpectrum: + * Values + * 0 - 0.5%, 3 - 1%, 8 - 1.5%, 18 - 2%, 28 - 3%, 34 - 4%, 39 - 5%, 44 - 6% + */ +enum fivr_spread_spectrum_ratio { + FIVR_SS_0_5 = 0, + FIVR_SS_1 = 3, + FIVR_SS_1_5 = 8, + FIVR_SS_2 = 18, + FIVR_SS_3 = 28, + FIVR_SS_4 = 34, + FIVR_SS_5 = 39, + FIVR_SS_6 = 44, +}; + struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -495,6 +511,23 @@ /* Platform Power Pmax */ uint16_t PsysPmax; + /* + * FivrRfiFrequency + * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. + * 0: Auto + * Range varies based on XTAL clock: + * 0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock + * 0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock + */ + uint32_t FivrRfiFrequency; + /* + * FivrSpreadSpectrum + * Set the Spread Spectrum Range. + * Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. + * Each Range is translated to an encoded value for FIVR register. + * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. + */ + uint8_t FivrSpreadSpectrum; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 9ed8acd..17edada 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -731,6 +731,14 @@ config->ext_fivr_settings.vnn_icc_max_ma; } +static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* transform from Hz to 100 KHz */ + s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz); + s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -761,6 +769,7 @@ fill_fsps_misc_power_params, fill_fsps_irq_params, fill_fsps_fivr_params, + fill_fsps_fivr_rfi_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/58878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34 Gerrit-Change-Number: 58878 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021