coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: David Wu, Zhuohao Lee, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > May I update the LED part in another commit? Verify the commit with correct LED settings? separate commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 5 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:42:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: David Wu, Zhuohao Lee, Alan Huang, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59149 ) Change subject: Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting" ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Ooph, I wish it wouldn't take so many revs of these intel docs 😞 -- To view, visit https://review.coreboot.org/c/coreboot/+/59149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388 Gerrit-Change-Number: 59149 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:41:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Malik Hsu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59135 ) Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge ...................................................................... Patch Set 5: Code-Review+2 (2 comments) File src/mainboard/google/brya/variants/primus/variant.c: https://review.coreboot.org/c/coreboot/+/59135/comment/e16a0be8_2a24570c PS5, Line 3: #include <console/console.h> unused? https://review.coreboot.org/c/coreboot/+/59135/comment/ad5dbd3e_ab1e4bb0 PS5, Line 6: #include <soc/pci_devs.h> unused? -- To view, visit https://review.coreboot.org/c/coreboot/+/59135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Gerrit-Change-Number: 59135 Gerrit-PatchSet: 5 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59004 ) Change subject: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59004/comment/3d8067e4_b05b6cc1 PS4, Line 9: of > `on` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Gerrit-Change-Number: 59004 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:38:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: enable ALC5682I-VS
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Malik Hsu, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59173 ) Change subject: mb/google/brya/variants/primus: enable ALC5682I-VS ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Gerrit-Change-Number: 59173 Gerrit-PatchSet: 9 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:37:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Nick Vaccaro, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 6: (3 comments) File src/mainboard/google/dedede/chromeos.c: https://review.coreboot.org/c/coreboot/+/59011/comment/d87d5354_737e26b7 PS6, Line 15: {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, > What is the relevance of passing a GPIO pin number and polarity here? Is the payload able (and platf […] depthcharge uses this data to re-read the current GPIO state if applicable (there is a `resample_at_runtime` flag in depthcharge). lb_gpio may only be used with depthcharge, but I wouldn't say that makes it obsolete 😊 File src/mainboard/google/eve/chromeos.c: https://review.coreboot.org/c/coreboot/+/59011/comment/b2d0c4d4_b4887728 PS6, Line 26: CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), > I understand this fills CRHW.GPIO sysfs subtree with chromeos_acpi driver. […] Yes, the `crossystem` userspace utility reads the ACPI package and then it can read the GPIOs again if desired: https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/ref… File src/mainboard/google/parrot/chromeos.c: https://review.coreboot.org/c/coreboot/+/59011/comment/9e5ce95c_99fecfcf PS6, Line 25: {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, > GPIO pin 101? Should these non-GPIO pins be -1 for virtual? maybe the PB was wired up to the PCH as well? not sure, but it does look fishy -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:33:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Felix Singer (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph, Tim Crawford, Sean Rhodes, SRIDHAR SIRICILLA, Tim Wawrzynczak, Evgeny Zinoviev, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 89: (2 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/06c197f3_5469ba43 PS88, Line 1067: me_state I would use another name here. While reading the code below, I thought this would be related to something of the me firmware but it's the value of the config option. Something like this: config_me_state or option_me_state https://review.coreboot.org/c/coreboot/+/52800/comment/0ba9e583_abffe832 PS88, Line 1085: enable > `disable_reply` ? I would name this `state_reply`. Maybe also switch the words so that the reader recognizes that `reply_state` and `reply_size` are related. -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 89 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:33:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: move SGX ACPI code to block/acpi
by Michael Niewöhner (Code Review) 11 Nov '21

11 Nov '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58925 ) Change subject: soc/intel: move SGX ACPI code to block/acpi ...................................................................... soc/intel: move SGX ACPI code to block/acpi Move SGX ACPI code to block/acpi. Also move the register definitions there, since they are misplaced in intelblocks/msr.h and are used only once anyways. Change-Id: I089d0ee97c37df2be060b5996183201bfa9b49ca Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58925 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/acpi/Makefile.inc A src/soc/intel/common/block/acpi/sgx.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/sgx/sgx.c 6 files changed, 68 insertions(+), 59 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c8eaad5..a6eb80d 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -4,3 +4,4 @@ ramstage-$(CONFIG_ACPI_BERT) += acpi_bert.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) += pep.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) += sgx.c diff --git a/src/soc/intel/common/block/acpi/sgx.c b/src/soc/intel/common/block/acpi/sgx.c new file mode 100644 index 0000000..7d9073d --- /dev/null +++ b/src/soc/intel/common/block/acpi/sgx.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <intelblocks/acpi.h> +#include <intelblocks/sgx.h> + +#define SGX_RESOURCE_ENUM_CPUID_LEAF 0x12 +#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF 0x2 +#define SGX_RESOURCE_ENUM_BIT 0x1 +#define SGX_RESOURCE_MASK_LO 0xfffff000UL +#define SGX_RESOURCE_MASK_HI 0xfffffUL + +static inline uint64_t sgx_resource(uint32_t low, uint32_t high) +{ + uint64_t val; + val = (uint64_t)(high & SGX_RESOURCE_MASK_HI) << 32; + val |= low & SGX_RESOURCE_MASK_LO; + return val; +} + +void sgx_fill_ssdt(void) +{ + bool epcs = false; + struct cpuid_result cpuid_regs; + uint64_t emna = 0, elng = 0; + + if (is_sgx_supported()) { + /* + * Get EPC base and size. + * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or + * higher for enumeration of SGX resources + */ + cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF, + SGX_RESOURCE_ENUM_CPUID_SUBLEAF); + + if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { + /* EPC section enumerated */ + epcs = true; + emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); + elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); + } + + printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n", + epcs, emna, elng); + } else { + printk(BIOS_DEBUG, "SGX: not supported.\n"); + } + + acpigen_write_scope("\\_SB.EPC"); + { + acpigen_write_name_byte("EPCS", epcs); + acpigen_write_name_qword("EMNA", emna); + acpigen_write_name_qword("ELNG", elng); + } + acpigen_pop_len(); +} diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 02a9da5..2d3136e 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -105,4 +105,7 @@ substate requirements */ void generate_acpi_power_engine_with_lpm(const struct soc_pmc_lpm *lpm); +/* Fill SSDT for SGX status, EPC base and length */ +void sgx_fill_ssdt(void); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 2e12bf0..e45b34d 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -108,13 +108,5 @@ #define SMRR_LOCK_SUPPORTED (1<<14) #define SGX_SUPPORTED (1<<2) -/* Intel SDM: Table 36-6. - * CPUID Leaf 12H, Sub-Leaf Index 2 or Higher for enumeration of - * SGX Resources. Same Table mentions about return values of the CPUID */ -#define SGX_RESOURCE_ENUM_CPUID_LEAF (0x12) -#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF (0x2) -#define SGX_RESOURCE_ENUM_BIT (0x1) -#define SGX_RESOURCE_MASK_LO (0xfffff000UL) -#define SGX_RESOURCE_MASK_HI (0xfffffUL) #endif /* SOC_INTEL_COMMON_MSR_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index fc7282f..3099faf 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -6,6 +6,11 @@ #include <soc/nvs.h> /* + * Check if SGX is supported + */ +int is_sgx_supported(void); + +/* * Configure core PRMRR. * PRMRR needs to configured first on all cores and then * call sgx_configure() for all cores to init SGX. @@ -17,7 +22,4 @@ */ void sgx_configure(void *unused); -/* Fill SSDT for SGX status, EPC base and length */ -void sgx_fill_ssdt(void); - #endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index d15fc0f..3008911 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -13,15 +12,7 @@ #include <soc/cpu.h> #include <soc/pci_devs.h> -static inline uint64_t sgx_resource(uint32_t low, uint32_t high) -{ - uint64_t val; - val = (uint64_t)(high & SGX_RESOURCE_MASK_HI) << 32; - val |= low & SGX_RESOURCE_MASK_LO; - return val; -} - -static int is_sgx_supported(void) +int is_sgx_supported(void) { struct cpuid_result cpuid_regs; msr_t msr; @@ -234,41 +225,3 @@ if (is_prmrr_approved()) activate_sgx(); } - -void sgx_fill_ssdt(void) -{ - bool epcs = false; - struct cpuid_result cpuid_regs; - uint64_t emna = 0, elng = 0; - - if (is_sgx_supported()) { - /* - * Get EPC base and size. - * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or - * Higher for enumeration of SGX Resources. Same Table mentions - * about return values of the CPUID - */ - cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF, - SGX_RESOURCE_ENUM_CPUID_SUBLEAF); - - if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { - /* EPC section enumerated */ - epcs = true; - emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); - elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); - } - - printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n", - epcs, emna, elng); - } else { - printk(BIOS_DEBUG, "SGX: not supported.\n"); - } - - acpigen_write_scope("\\_SB.EPC"); - { - acpigen_write_name_byte("EPCS", epcs); - acpigen_write_name_qword("EMNA", emna); - acpigen_write_name_qword("ELNG", elng); - } - acpigen_pop_len(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/58925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I089d0ee97c37df2be060b5996183201bfa9b49ca Gerrit-Change-Number: 58925 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Sean Rhodes (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph, Tim Crawford, SRIDHAR SIRICILLA, Tim Wawrzynczak, Evgeny Zinoviev, Felix Held. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 89: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/928840c9_0d2a6c4e PS88, Line 1085: enable > `disable_reply` ? Doh! Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 89 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:22:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59004 ) Change subject: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59004/comment/9956ec77_b49a75b5 PS4, Line 9: of `on` -- To view, visit https://review.coreboot.org/c/coreboot/+/59004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Gerrit-Change-Number: 59004 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:20:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021