Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Rob Barnes, Yu-Ping Wu, Felix Held.
Hello Jason Glenesk, build bot (Jenkins), Marshall Dawson, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59082
to look at the new patch set (#4).
Change subject: mb/google/guybrush: Add variant_espi_gpio_table
......................................................................
mb/google/guybrush: Add variant_espi_gpio_table
Add separate gpio table for early eSPI bus init. Remove espi GPIO from
early_gpio_table. This allows for initializing eSPI separately from
other GPIOs. Simplify verstage_mainboard_early_init.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/verstage.c
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
5 files changed, 56 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59082/4
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Gerrit-Owner: Rob Barnes <robbarnes(a)google.com>
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59229 )
Change subject: Documentation: Remove references to "private" changes on Gerrit
......................................................................
Documentation: Remove references to "private" changes on Gerrit
Private changes on Gerrit are a tricky beast in that they're well hidden
in the UI and a few other places but still reachable with little effort
when you want to dig for private changes.
Therefore review.coreboot.org disabled that feature, so update the
documentation to follow.
Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M Documentation/getting_started/gerrit_guidelines.md
M Documentation/tutorial/part2.md
2 files changed, 3 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59229/1
diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md
index 8c91615..6a5ba37 100644
--- a/Documentation/getting_started/gerrit_guidelines.md
+++ b/Documentation/getting_started/gerrit_guidelines.md
@@ -191,14 +191,10 @@
git push origin HEAD:refs/for/master%wip
* When pushing patches that are not for submission, these should be marked
-as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
-private changes, so that only explicitly added reviewers will see them. These
-sorts of patches are frequently posted as ideas or RFCs for the community
-to look at. To push a private change, use the command:
- git push origin HEAD:refs/for/master%private
+as such. This can be done in the title ‘[DONOTSUBMIT]’ or by pushing as WIP.
* Multiple push options can be combined:
- git push origin HEAD:refs/for/master%private,wip,topic=experiment
+ git push origin HEAD:refs/for/master%wip,topic=experiment
* Respond to anyone who has taken the time to review your patches, even if
it's just to say that you disagree. While it may seem annoying to address a
diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md
index 4ac8574..693e36b 100644
--- a/Documentation/tutorial/part2.md
+++ b/Documentation/tutorial/part2.md
@@ -170,10 +170,7 @@
you to take back your commit and amend it.
When you are done with your commit, run `git push` to push your commit to
-coreboot.org. **Note:** To submit as a private patch, use
-`git push origin HEAD:refs/for/master%private`. Submitting as a private patch
-means that your commit will be on review.coreboot.org, but is only visible to
-yourself and those you add as reviewers.
+coreboot.org.
This has been a quick primer on how to submit a change to Gerrit for review
using git. You may wish to review the [Gerrit code review workflow
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59082 )
Change subject: mb/google/guybrush: Add variant_espi_gpio_table
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/verstage.c:
https://review.coreboot.org/c/coreboot/+/59082/comment/55176a93_4beee049
PS3, Line 16: if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
I believe the condition is inverted. It should be actually:
```
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
return;
```
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 )
Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
Patch Set 11:
(3 comments)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/58870/comment/e18b32dc_a4985c27
PS9, Line 224: rv = verstage_soc_early_init();
: if (rv) {
: printk(BIOS_DEBUG, "verstage_soc_early_init failed rv:%d\n", rv);
: return POSTCODE_INIT_TPM_FAILED;
: }
> Maybe we fork too early in Main. […]
Done
https://review.coreboot.org/c/coreboot/+/58870/comment/3a1970e1_dd6c69c1
PS9, Line 230: verstage_mainboard_espi_init();
: /* verstage_soc_init should init i2c and eSPI */
: verstage_soc_init();
: /*
: * verstage_mainboard_tpm_init may check board_id which depends on eSPI,
: * so it must come after verstage_mainboard_espi_init and verstage_soc_init.
: */
: verstage_mainboard_tpm_init();
> Can we just make this the default flow? […]
I moved TPM and eSPI gpios out of esarly_gpio_table as suggested.
I did not move TPM and eSPI init into verstage_mainboard_early_init because I want to avoid initializing the early_gpio_table. I also want to avoid having two calls to svc_get_boot_mode.
https://review.coreboot.org/c/coreboot/+/58870/comment/386c4d21_77989859
PS9, Line 280:
> nit: space
Done
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Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Yu-Ping Wu, Felix Held.
Hello Jason Glenesk, build bot (Jenkins), Marshall Dawson, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59083
to look at the new patch set (#3).
Change subject: mb/google/guybrush: Add variant_tpm_gpio_table
......................................................................
mb/google/guybrush: Add variant_tpm_gpio_table
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from
early_gpio_table. This allows for initializing TPM gpios separately from
other gpios.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/variants/guybrush/gpio.c
M src/mainboard/google/guybrush/variants/nipperkin/gpio.c
M src/mainboard/google/guybrush/verstage.c
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
7 files changed, 87 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59083/3
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Hello Jason Glenesk, build bot (Jenkins), Marshall Dawson, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59082
to look at the new patch set (#3).
Change subject: mb/google/guybrush: Add variant_espi_gpio_table
......................................................................
mb/google/guybrush: Add variant_espi_gpio_table
Add separate gpio table for early eSPI bus init. Remove espi GPIO from
early_gpio_table. This allows for initializing eSPI separately from
other GPIOs. Simplify verstage_mainboard_early_init.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/verstage.c
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
5 files changed, 56 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59082/3
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Change subject: mb/google/guybrush: Add variant_tpm_gpio_table
......................................................................
Patch Set 2:
(1 comment)
File src/security/vboot/vboot_common.h:
https://review.coreboot.org/c/coreboot/+/59083/comment/364f8f6c_7dea2ea5
PS1, Line 47: verstage_mainboard_tpm_init
> Same as the previous one. Move to a cezanne specific header.
Done
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Change subject: mb/google/guybrush: Add variant_espi_gpio_table
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/guybrush/verstage.c:
https://review.coreboot.org/c/coreboot/+/59082/comment/a3a1dbec_288ed9ad
PS1, Line 64: gpio_configure_pads
> Do we need to setup the I2C TPM GPIOs?
That's handled in follow on CL.
File src/security/vboot/vboot_common.h:
https://review.coreboot.org/c/coreboot/+/59082/comment/1985b416_dd42a5f3
PS1, Line 46: verstage_mainboard_espi_init
> I would put this in a Cezanne specific header. […]
psp_verstage.h
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Change subject: mb/google/guybrush: Add variant_tpm_gpio_table
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/59083/comment/dea71711_b95f381d
PS1, Line 260: PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
> How about configuring both GPIO_3 and GPIO_85 as PAD_INT in verstage. […]
I get back that comment. That will not work because this table is going to be used in S0i3 resume and bootblock will not come in the picture to fix the configuration.
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59083 )
Change subject: mb/google/guybrush: Add variant_tpm_gpio_table
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Patch Set 2:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/59083/comment/f923cdcd_2276120f
PS1, Line 260: PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
How about configuring both GPIO_3 and GPIO_85 as PAD_INT in verstage. Given that GPIO_3 is supposed to be GPO, I think it should not be receiving any interrupt.
Later when x86 comes out of reset and enters bootblock, GPIOs can be configured correctly. WDYT?
This will simplify the number of tables used. I think Nipperkin BID1 does exactly that - configure both the GPIOs as PAD_INT.
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