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Change subject: soc/amd/psp_verstage: Reboot on verstage_soc_early_init fail
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/59017/comment/a17d5d55_0c9fdc57
PS1, Line 224:
> What will PSP do with a non-zero retval in svc_exit? […]
Agree, doing a vboot_reboot is worth a short.
It seems pretty arbitrary that we are checking for errors on vertage_soc_early_init and not on most of the other calls. I think we should be checking for errors at each step here. I can open a separate bug.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
......................................................................
soc/amd/psp_verstage: Init TPM on S0i3 resume
Add option to initialize the TPM in PSP verstage during s0i3 resume.
This is needed if the TPM is reset in s0i3. FSDL is handling
restoring everything else, so only the minimum TPM initialization is done.
BUG=b:200578885,b:197965075
TEST=Multiple cycles of S0i3 suspend resume. 50-100ms of additional delay.
BRANCH=None
Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/Kconfig
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
4 files changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/10
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Change subject: mb/google/guybrush: Add variant_tpm_gpio_table
......................................................................
mb/google/guybrush: Add variant_tpm_gpio_table
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from
early_gpio_table. This allows for initializing TPM gpios separately from
other gpios.
BUG=b:200578885
BRANCH=None
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Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/variants/guybrush/gpio.c
M src/mainboard/google/guybrush/variants/nipperkin/gpio.c
M src/mainboard/google/guybrush/verstage.c
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
7 files changed, 86 insertions(+), 17 deletions(-)
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Change subject: mb/google/guybrush: Add variant_espi_gpio_table
......................................................................
mb/google/guybrush: Add variant_espi_gpio_table
Add separate gpio table for early eSPI bus init. Remove espi GPIO from
early_gpio_table. This allows for initializing eSPI separately from
other GPIOs. Simplify verstage_mainboard_early_init.
BUG=b:200578885
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Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/verstage.c
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
5 files changed, 56 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59082/2
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Change subject: soc/amd/psp_verstage: Reboot on verstage_soc_early_init fail
......................................................................
soc/amd/psp_verstage: Reboot on verstage_soc_early_init fail
Calling reboot_into_recovery with NULL context fails. Initializing ctx
early also fails because the cmos is not ready until after
verstage_soc_early_init. So just reboot and hope for the best.
BUG=None
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---
M src/soc/amd/common/psp_verstage/include/psp_verstage.h
M src/soc/amd/common/psp_verstage/psp_verstage.c
2 files changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/59017/3
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Change subject: soc/amd/psp_verstage: Get vb2_context early
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/59017/comment/4ee75964_9ff7672c
PS1, Line 224:
> Whatever we choose between `svc_exit`, `die` or `assert` I'm okay with it if it's not a `reboot_into […]
What will PSP do with a non-zero retval in svc_exit?
Will triggering a board_reset() help to recover from the scenario? If so we can just call vboot_reboot() hoping that in the next boot cycle we get lucky.
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 )
Change subject: soc/intel/alderlake: Disable VT-d for early silicons
......................................................................
Patch Set 3: -Code-Review
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/59191/comment/78e26db8_eab7ffa8
PS3, Line 264: cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1
> So if the first part is false, then this is always true since everything greater than 0 is evaluated […]
Ooph my eyes are broken today, thanks Felix 😄
suggestion:
```
const uint32_t cpuid = cpu_get_cpuid();
if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1)
```
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Change subject: soc/intel/common/cse: Add support to get CSME timestamps
......................................................................
soc/intel/common/cse: Add support to get CSME timestamps
This command retrieves a set of early boot performance
timestamps CSME collected while the platform last boot flow
BUG=b:182575295
TEST=Verify CSME timestamps after S3 and boot.
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66
---
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 94 insertions(+), 0 deletions(-)
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Change subject: timestamp: Add new helper functions
......................................................................
timestamp: Add new helper functions
1. timestamp_rewind_base
This function will rewind base_time in timestamp table using the delta provided in base_freq_mhz.
* 1. Calculate base_delta_tick in ts->tick_freq_mhz using base_delta * ts->tick_freq_mhz / base_freq_mhz.
* 2. Update all entries in timestamp table by adding base_delta_tick
* 3. Update ts->base_time as ts->base_time - base_delta_tick
2. timestamp_add_relative
* This function will add a new entry to timestamp table using the time_from_base expressed in freq_mhz
* 1. Calculate time_from_base in ts->tick_freq_mhz using time_from_base * ts->tick_freq_mhz / freq_mhz.
* 2. Call timestamp_add_table_entry using ts_table, id, time_from_base_tick
BUG=b:182575295
TEST=Rewind the base timestamp, add relative timestamps and verify cbmem -t output
Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
---
M src/include/timestamp.h
M src/lib/timestamp.c
2 files changed, 78 insertions(+), 0 deletions(-)
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 )
Change subject: soc/intel/alderlake: Disable VT-d for early silicons
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Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/59191/comment/cc3adad9_2860c68a
PS3, Line 264: cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1
> Um, doesn't the comparison only apply for the first part?
So if the first part is false, then this is always true since everything greater than 0 is evaluated to true.
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