Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59196 )
Change subject: Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set
......................................................................
Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set
Show the DEBUG_FUNC option if COSOLE_OVERRIDE_LOGLEVEL is set, or it
will never be available for some mainboards.
This was missed in commit cf3dcd6d2975673622c3272e0d7f3e421051fe74
Change-Id: Id2ef287fb39989007f28fc6475209eda0a63c792
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
M src/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/59196/1
diff --git a/src/Kconfig b/src/Kconfig
index e1d0c00..44e84bf 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1179,7 +1179,7 @@
endif
config DEBUG_FUNC
- bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
+ bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
default n
help
This option enables additional function entry and exit debug messages
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58925 )
Change subject: soc/intel: move SGX ACPI code to block/acpi
......................................................................
Patch Set 6: Code-Review+2
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Change subject: driver/intel/mipi_camera: Add support for _DSC field
......................................................................
Patch Set 9: Code-Review+1
(1 comment)
File src/drivers/intel/mipi_camera/chip.h:
https://review.coreboot.org/c/coreboot/+/58767/comment/2366b56b_80371610
PS9, Line 25: #define POWER_STATE_D0 0
: #define POWER_STATE_D1 1
: #define POWER_STATE_D2 2
: #define POWER_STATE_D3_HOT 3
: #define POWER_STATE_D3_COLD 4
Do we really need these or can we reuse
`ACPI_DEVICE_SLEEP_D0`
through
`ACPI_DEVICE_SLEEP_D3_COLD`
?
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Change subject: security/vboot: Add NVRAM counter for TPM 2.0
......................................................................
Patch Set 3:
(7 comments)
Patchset:
PS2:
> Could you point me to the design doc?
go/rollback-2.0
Patchset:
PS3:
> Thank you for reviewing! […]
Yes, for most devices ToT firmware should work fine. You should test on ToT first and then worry about backporting once that patch lands.
Note that testing TPM factory initialization is tricky because you have to fully erase all TPM spaces manually to get it to run again. To do that you have to boot a test image in recovery mode and use manual tpmc undefinespace commands. Deleting the "firmware" space (the one created with pcr0_allowed_policy) is even more tricky, you can find instructions in b/140958855. Also be aware that the patch which added that policy only landed in October 2020, so this will only work on Chromebooks that have had their very first boot (in the factory) with firmware that included that patch.
File src/security/vboot/antirollback.h:
https://review.coreboot.org/c/coreboot/+/59097/comment/b2880549_a424f776
PS3, Line 100: uint32_t enterprise_rollback_create_counter(void);
This function no longer needs to be exported now.
File src/security/vboot/secdata_mock.c:
https://review.coreboot.org/c/coreboot/+/59097/comment/c3e280b7_63e0a3e3
PS3, Line 73: vb2_error_t enterprise_rollback_create_counter(void)
(...and then you won't need a mock for it...)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/59097/comment/072290a4_84bb3322
PS3, Line 150: .TPMA_NV_NO_DA = 1,
Actually, now that I'm comparing this more with the ZTE counter space I'm also wondering why it has NV_BITS and NV_NO_DA set and whether this should have those as well. I think BITS was about something else (I think the ZTE design needed the counter to start at 0 which isn't really the case for this), but NO_DA might still be a good idea. Hopefully Andrey can offer some more guidance.
https://review.coreboot.org/c/coreboot/+/59097/comment/6ec40f60_0853b469
PS3, Line 438: NULL, 0)
Soo... actually, wait a second. The only reason you're doing this whole counter business is that you want to protect against a post factum, invasive attack (which includes firmware reflashing to fake the PCR0 sealing). Then not having a policy here would be defeat that whole purpose, because the attacker in that scenario could replace the firmware with something that simply deletes and recreates this counter with platform authorization.
So I think what you actually want is to use unsatisfiable_policy here (and set TPMA_NV_POLICY_DELETE to actually make it take effect), same as the ZTE RMA bytes counter.
https://review.coreboot.org/c/coreboot/+/59097/comment/435aacb5_ff74c992
PS3, Line 540: uint32_t enterprise_rollback_create_counter(void)
...and won't need this anymore.
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58926 )
Change subject: soc/amd/common/block: Add spi_hw mutex
......................................................................
Patch Set 2: Code-Review+2
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 )
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 86:
(6 comments)
Patchset:
PS81:
> On system76/oryp8, it fails to enable the IME: […]
Done
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/7e640e43_d4bf60c7
PS85, Line 1057: int send;
: int result;
> Declare variables at the beginning of that function.
Done
https://review.coreboot.org/c/coreboot/+/52800/comment/4319ce5c_9ae38284
PS85, Line 1062: uint32_t rule_id;
> When setting to Normal mode, the reply does not have a rule_id.
Done
https://review.coreboot.org/c/coreboot/+/52800/comment/e58fc8c3_22cb3b3a
PS85, Line 1060: struct state_reply {
: struct mkhi_hdr hdr;
: uint32_t rule_id;
: } __packed;
> Not sure about this. I would put this at the beginning too.
That's much better
https://review.coreboot.org/c/coreboot/+/52800/comment/ca62530d_e9640ef4
PS85, Line 1065: struct state_reply reply;
:
: size_t reply_size;
> Declare variables at the beginning of that function.
Done
https://review.coreboot.org/c/coreboot/+/52800/comment/66a784e7_9ea99417
PS85, Line 1109:
> Remove empty line
Done
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59122 )
Change subject: Doc/releases/coreboot-4.16-relnotes.md: Fix typo
......................................................................
Doc/releases/coreboot-4.16-relnotes.md: Fix typo
Change-Id: I7189ac62d5ec826cf0377712941ba227362c1e09
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59122
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
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---
M Documentation/releases/coreboot-4.16-relnotes.md
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Felix Held: Looks good to me, approved
Felix Singer: Looks good to me, approved
diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md
index 3c7eef2..a4c7af2 100644
--- a/Documentation/releases/coreboot-4.16-relnotes.md
+++ b/Documentation/releases/coreboot-4.16-relnotes.md
@@ -1,7 +1,7 @@
Upcoming release - coreboot 4.16
================================
-The 4.16 release is planned for Februrary, 2022.
+The 4.16 release is planned for February, 2022.
We are increasing the frequency of releases in order to enable others to release quarterly on
a fresher version of coreboot.
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59121 )
Change subject: Doc/releases: Fix coreboot 4.15 release notes
......................................................................
Doc/releases: Fix coreboot 4.15 release notes
coreboot 4.15 has just been released, so it's neither "upcoming" nor
"planned" anymore.
Change-Id: I287e40deec5877764e511885e3268b606caff597
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59121
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M Documentation/releases/coreboot-4.15-relnotes.md
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Felix Held: Looks good to me, approved
Felix Singer: Looks good to me, approved
Jason Glenesk: Looks good to me, but someone else must approve
diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md
index d1fac52..087513e 100644
--- a/Documentation/releases/coreboot-4.15-relnotes.md
+++ b/Documentation/releases/coreboot-4.15-relnotes.md
@@ -1,7 +1,7 @@
-Upcoming release - coreboot 4.15
+coreboot 4.15
================================
-The 4.15 release is planned for November 5th, 2021.
+coreboot 4.15 was released on November 5th, 2021.
Since 4.14 there have been more than 2597 new commits by more than 219 developers.
Of these, over 73 contributed to coreboot for the first time.
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