coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons
by Felix Singer (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Abhijeet Rao, Maulik V Vaghela, Meera Ravindranath, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 ) Change subject: soc/intel/alderlake: Disable VT-d for early silicons ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/59191/comment/ec8ab603_157ee91e PS3, Line 264: cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1 Um, doesn't the comparison only apply for the first part? -- To view, visit https://review.coreboot.org/c/coreboot/+/59191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Gerrit-Change-Number: 59191 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 20:39:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Karthik Ramasubramanian (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Julius Werner, Andrey Petrov, Yu-Ping Wu, Patrick Rudolph, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58253 ) Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c: PS7: > I think we should stay it unchanged since it is a __weak fallback, […] Yes it can be removed. Either gpio_baseboard_trembyle.c or gpio_baseboard_dalboz.c will be built and not both. I dont see any overrides in variants of the concerned baseboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/58253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Gerrit-Change-Number: 58253 Gerrit-PatchSet: 7 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 20:35:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hsuan-ting Chen <roccochen(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google,intel: Split chromeos.c files
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 ) Change subject: mb/google,intel: Split chromeos.c files ...................................................................... Patch Set 6: (3 comments) File src/mainboard/google/dedede/chromeos.c: https://review.coreboot.org/c/coreboot/+/59011/comment/152015c0_1269958e PS6, Line 15: {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, > depthcharge uses this data to re-read the current GPIO state if applicable (there is a `resample_at_ […] Ack File src/mainboard/google/eve/chromeos.c: https://review.coreboot.org/c/coreboot/+/59011/comment/e9d213c1_b7f81501 PS6, Line 26: CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), > Yes, the `crossystem` userspace utility reads the ACPI package and then it can read the GPIOs again […] Ah, thanks for the link. From ReadGPIO() in crosssyste_arch.c line 790_ /* Do not attempt to read GPIO that is set to -1 in ACPI */ if (controller_num == 0xFFFFFFFF) return -1; To me that looks like CROS_GPIO_VIRTUAL ignores polarity and name, and return value is the same as if the virtual GPIO was never present in CRHW.GPIO. File src/mainboard/google/parrot/chromeos.c: https://review.coreboot.org/c/coreboot/+/59011/comment/eb8bcef0_8cc133df PS6, Line 25: {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, > maybe the PB was wired up to the PCH as well? not sure, but it does look fishy Literal GPIOs 100 and 101 appeared somewhere else too. -- To view, visit https://review.coreboot.org/c/coreboot/+/59011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Gerrit-Change-Number: 59011 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 20:29:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by Subrata Banik (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59209 to look at the new patch set (#2). Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... soc/intel/../thermal: Refactor PCH Thermal Configuration common API Thermal configuration has evolved over PCH generations where latest PCH has provided an option to allow thermal configuration using PMC PWRMBASE registers. This patch adds an option for impacted SoC to select the Kconfig for allowing thermal configuration using PMC PCH MMIO space. TODO: Combine all changes for now till we split it meaningfully. BUG=b:193774296 Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/thermal.c 3 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
by Subrata Banik (Code Review) 11 Nov '21

11 Nov '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API ...................................................................... soc/intel/../thermal: Refactor PCH Thermal Configuration common API Thermal configuration has evolved over PCH generations where latest PCH has provided an option to allow thermal configuration using PMC PWRMBASE registers. This patch adds an option for impacted SoC to select the Kconfig for allowing thermal configuration using PMC PCH MMIO space. TODO: Combine all changes for now till we split it meaningfully. Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/thermal.c 3 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 58b9051..796f7bc 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -68,6 +68,8 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI diff --git a/src/soc/intel/common/block/thermal/Kconfig b/src/soc/intel/common/block/thermal/Kconfig index 0605176..d723f25 100644 --- a/src/soc/intel/common/block/thermal/Kconfig +++ b/src/soc/intel/common/block/thermal/Kconfig @@ -3,3 +3,11 @@ default n help This option allows to configure PCH thermal registers for supported PCH. + +config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC + bool + depends on SOC_INTEL_COMMON_BLOCK_THERMAL + default n + help + This option allows to configure PCH thermal registers using PMC PWRMBASE + for chipsets since Tiger Lake PCH. diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index f886995..b5b7be8 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -40,8 +40,8 @@ return ltt_value; } -/* Enable thermal sensor power management */ -void pch_thermal_configuration(void) +/* Enable thermal sensor power management using PCI Thermal device */ +static void pch_pci_thermal_configuration(void) { uint16_t reg16; uintptr_t thermalbar; @@ -74,3 +74,27 @@ reg16 |= pch_get_ltt_value(dev); write16((uint16_t *)thermalbar_pm, reg16); } + +/* Enable thermal sensor power management using PMC PCH device */ +static void pch_pmc_thermal_configuration(void) +{ + +} + +/* + * Thermal configuration has evolved over time. With older platform the + * thermal device is sitting over PCI and allow to configure its configuration + * register by accessing the PCI configuration space or MMIO space. + * + * Since Tiger Lake, thermal registers are being moved behind the PMC PCI device + * hence, accessing thermal configuration registers would need making access + * to PWRMBASE. In this case SoC Kconfig to select + * SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to allow thermal configuration. + */ +void pch_thermal_configuration(void) +{ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC)) + return pch_pmc_thermal_configuration(); + + pch_pci_thermal_configuration(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Sean Rhodes (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph, Tim Crawford, SRIDHAR SIRICILLA, Tim Wawrzynczak, Evgeny Zinoviev, Felix Held. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 90: (3 comments) Patchset: PS90: Re-tested KBL, CML and TGL - all switching back and forth as they should. File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/09cb8e0a_24a62e03 PS88, Line 1067: me_state > I would use another name here. […] That alright? https://review.coreboot.org/c/coreboot/+/52800/comment/cb92c8f2_4cdcb7da PS88, Line 1085: enable > I would name this `state_reply`. […] Slightly inefficient but clear, cool? -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 90 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 20:14:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Subrata Banik, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 ) Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... Patch Set 10: Code-Review+1 (2 comments) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/58351/comment/e0b56ecb_f38b2405 PS7, Line 461: int gpio_lock_multiple_pads(const struct gpio_lock_config *pads_a, const size_t count_a, : const struct gpio_lock_config *pads_b, const size_t count_b) > I had thought about that as well, seems much more straight-foward to have the routine support lockin […] That seems fine to me, the unlocking/locking of PCR 2 times should not be terrible. File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/58351/comment/cc0cc3fe_62624fe5 PS7, Line 328: const struct gpio_lock_config *soc_gpios; : const struct gpio_lock_config *mb_gpios; : size_t soc_gpio_num; : size_t mb_gpio_num; : : /* get list of gpios from SoC, exit if SoC does not export a list */ : soc_gpios = soc_gpio_lock_config(&soc_gpio_num); : : /* get list of gpios from mainboard, it's ok if mb does not export a list */ : mb_gpios = mb_gpio_lock_config(&mb_gpio_num); : : /* Lock all mainboard and soc requested gpios */ : gpio_lock_multiple_pads(soc_gpios, soc_gpio_num, mb_gpios, mb_gpio_num); > so you could just use malloc() here to allocate a list long enough to store both and not have the aw […] Or call it twice ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:52:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Add thermal sensor settings
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: David Wu, Sumeet R Pawnikar, Peter Ou. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59089 ) Change subject: mb/google/brya/var/kano: Add thermal sensor settings ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Gerrit-Change-Number: 59089 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:48:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Abhijeet Rao, Maulik V Vaghela, Meera Ravindranath, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 ) Change subject: soc/intel/alderlake: Disable VT-d for early silicons ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/59191/comment/dd407148_15930524 PS3, Line 268: m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; nit: blank line after `}` -- To view, visit https://review.coreboot.org/c/coreboot/+/59191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Gerrit-Change-Number: 59191 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:47:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
by Tim Wawrzynczak (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Subrata Banik, Meera Ravindranath, Angel Pons, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58811 ) Change subject: Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods" ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58811/comment/8d65ad63_72066230 PS4, Line 22: disabled > any regression in power number ? ping 😊 Patchset: PS5: ping, Maulik -- To view, visit https://review.coreboot.org/c/coreboot/+/58811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf Gerrit-Change-Number: 58811 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 19:43:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021