coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/primus: Disable autonomous GPIO power management
by Paul Fagerburg (Code Review) 12 Nov '21

12 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59079 ) Change subject: mb/google/brya/var/primus: Disable autonomous GPIO power management ...................................................................... mb/google/brya/var/primus: Disable autonomous GPIO power management Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201054849 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb 1 file changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index c4debb4..81dc1c0 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -22,7 +22,16 @@ end chip soc/intel/alderlake - + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733" 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Gerrit-Change-Number: 59079 Gerrit-PatchSet: 4 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch
by Sugnan Prabhu S (Code Review) 12 Nov '21

12 Nov '21

Sugnan Prabhu S has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59265 ) Change subject: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/59265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9cef8d03b73694764c6a4a18706f4a44555838a Gerrit-Change-Number: 59265 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch
by Sugnan Prabhu S (Code Review) 12 Nov '21

12 Nov '21

Sugnan Prabhu S has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/59265 ) Change subject: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/59265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9cef8d03b73694764c6a4a18706f4a44555838a Gerrit-Change-Number: 59265 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch
by Sugnan Prabhu S (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Patrick Rudolph. Sugnan Prabhu S has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/59265 ) Change subject: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/59265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9cef8d03b73694764c6a4a18706f4a44555838a Gerrit-Change-Number: 59265 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch
by Sugnan Prabhu S (Code Review) 12 Nov '21

12 Nov '21

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59265 ) Change subject: [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch ...................................................................... [DO-NOT-MERGE] Enable crashlog UPDs always for socwatch Change-Id: Ia9cef8d03b73694764c6a4a18706f4a44555838a --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/59265/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index be71a02..13a0957 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -309,7 +309,7 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; /* CrashLog config */ - m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); + m_cfg->CpuCrashLogDevice = 1; m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; } -- To view, visit https://review.coreboot.org/c/coreboot/+/59265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9cef8d03b73694764c6a4a18706f4a44555838a Gerrit-Change-Number: 59265 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci_device.c: Improve pci_bridge_route() readability
by Arthur Heymans (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Arthur Heymans, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59131 ) Change subject: device/pci_device.c: Improve pci_bridge_route() readability ...................................................................... Patch Set 2: (2 comments) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/59131/comment/225b2d73_34cd5407 PS1, Line 1337: u32 raw; : struct { : u8 primary; : u8 secondary; : u8 subordinate; : u8 _latency; : } __packed; > This is not portable. As PCI is a little endian bus, I think this is more portable than the existing code. https://review.coreboot.org/c/coreboot/+/59131/comment/e220b9ba_d18410c6 PS1, Line 1356: parent > link Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Gerrit-Change-Number: 59131 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 14:16:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_device.c: Improve pci_bridge_route() readability
by Arthur Heymans (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59131 to look at the new patch set (#2). Change subject: device/pci_device.c: Improve pci_bridge_route() readability ...................................................................... device/pci_device.c: Improve pci_bridge_route() readability Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Using an union/struct removes the need to juggle with bitwise operations. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/pci_device.c 1 file changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/59131/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Gerrit-Change-Number: 59131 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by Rob Barnes (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Raul Rangel, Andrey Pronin, Kangheui Won, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Glenesk, Andrey Pronin, Raul Rangel, Marshall Dawson, Kangheui Won, Julius Werner, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58870 to look at the new patch set (#14). Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... soc/amd/psp_verstage: Init TPM on S0i3 resume Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. BUG=b:200578885,b:197965075 TEST=Multiple cycles of S0i3 suspend resume. 50-100ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 3 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 14 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/brask: Set PL and PsysPL
by Alan Huang (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/variants/brask: Set PL and PsysPL ...................................................................... Patch Set 12: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 12 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 13:44:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_device.c: Improve pci_bridge_route() readability
by Angel Pons (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59131 ) Change subject: device/pci_device.c: Improve pci_bridge_route() readability ...................................................................... Patch Set 1: (2 comments) File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/59131/comment/e62581c4_e5dba8b9 PS1, Line 1337: u32 raw; : struct { : u8 primary; : u8 secondary; : u8 subordinate; : u8 _latency; : } __packed; This is not portable. https://review.coreboot.org/c/coreboot/+/59131/comment/702b023a_64ece160 PS1, Line 1356: parent link -- To view, visit https://review.coreboot.org/c/coreboot/+/59131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Gerrit-Change-Number: 59131 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 12 Nov 2021 13:36:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021