coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
by Meera Ravindranath (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Nick Vaccaro, Ronak Kanabar, Patrick Rudolph. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 ) Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/52730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52730 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 11:02:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Varshit B Pandya (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58767 ) Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... Patch Set 10: (1 comment) File src/drivers/intel/mipi_camera/chip.h: https://review.coreboot.org/c/coreboot/+/58767/comment/20abe731_2dcf55ff PS9, Line 25: #define POWER_STATE_D0 0 : #define POWER_STATE_D1 1 : #define POWER_STATE_D2 2 : #define POWER_STATE_D3_HOT 3 : #define POWER_STATE_D3_COLD 4 > Do we really need these or can we reuse […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 11:01:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEV...
by Varshit B Pandya (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak. Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59260 ) Change subject: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD ...................................................................... mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/59260/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index ce9ba37..125c7a1 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -266,6 +266,7 @@ register "num_freq_entries" = "1" register "link_freq[0]" = "DEFAULT_LINK_FREQ" register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "has_power_resource" = "1" #Controls @@ -301,6 +302,7 @@ register "acpi_name" = ""CAM0"" register "chip_name" = ""Hi-556 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "ssdb.lanes_used" = "2" register "ssdb.link_used" = "1" @@ -341,8 +343,19 @@ register "acpi_name" = ""NVM0"" register "chip_name" = ""M24C64X"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_UCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/59260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Gerrit-Change-Number: 59260 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Varshit B Pandya (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Paul Menzel, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58767 to look at the new patch set (#10). Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... driver/intel/mipi_camera: Add support for _DSC field The _DSC (Device State for Configuration) object evaluates to an integer may be used to tell Linux the highest allowed D state for a device during probe. The support for _DSC requires support from the kernel bus type if the bus driver normally sets the device in D0 state for probe. The D states and thus also the allowed values for _DSC are listed below. Number State Description 0 D0 Device fully powered on 1 D1 2 D2 3 D3hot 4 D3cold Off More details can be found here https://lkml.org/lkml/2021/10/25/397 BUG=none BRANCH=none TEST=Add corresponding field in brya, boot and dump SSDT to check if _DSC field is as per expectation. Name (_ADR, Zero) // _ADR: Address Name (_HID, "OVTI8856") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_DSC, 0, NotSerialized) { Return (0x04) } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/58767/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree
by Mario Scheithauer (Code Review) 12 Nov '21

12 Nov '21

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59259 ) Change subject: mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree ...................................................................... mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree With latest hardware revision all clock outputs will be used on this mainboard. For this reason set all clock source mappings to 'PCIE_CLK_FREE' to have a free running clock. Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59259/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 39789be..ca90557 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -55,9 +55,9 @@ register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" -- To view, visit https://review.coreboot.org/c/coreboot/+/59259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Gerrit-Change-Number: 59259 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/lint: Exclude coreboot-configurator directory from checkpatch
by Sean Rhodes (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59096 to look at the new patch set (#5). Change subject: util/lint: Exclude coreboot-configurator directory from checkpatch ...................................................................... util/lint: Exclude coreboot-configurator directory from checkpatch The linter doesn't work well with CPP so exclude. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097 --- M util/lint/lint-007-checkpatch M util/lint/lint-extended-015-final-newlines 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/59096/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097 Gerrit-Change-Number: 59096 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: add GIC pre-initialization function
by Yu-Ping Wu (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59252 ) Change subject: soc/mediatek/mt8186: add GIC pre-initialization function ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bf439d0d9e1ca7130a69b9006b957afca8b133c Gerrit-Change-Number: 59252 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 10:08:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add support for PMIC MT6366
by build bot (Jenkins) (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59245 ) Change subject: soc/mediatek/mt8186: Add support for PMIC MT6366 ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133125): https://review.coreboot.org/c/coreboot/+/59245/comment/3f5d64d8_ec37b340 PS3, Line 708: while (!stopwatch_expired(&voltage_settled)) suspect code indent for conditional statements (8, 49) -- To view, visit https://review.coreboot.org/c/coreboot/+/59245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Gerrit-Change-Number: 59245 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 09:40:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/lint: Exclude coreboot-configurator directory from checkpatch
by Sean Rhodes (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Martin Roth. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59096 ) Change subject: util/lint: Exclude coreboot-configurator directory from checkpatch ...................................................................... Patch Set 4: (1 comment) File util/lint/lint-extended-007-checkpatch: https://review.coreboot.org/c/coreboot/+/59096/comment/889b72ba_57798469 PS2, Line 15: util/coreboot-configurator > You don't want to add it here, this is a list of directories TO run checkpatch on. Thanks :) -- To view, visit https://review.coreboot.org/c/coreboot/+/59096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097 Gerrit-Change-Number: 59096 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 09:22:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: Remove _BCL from acpigen
by Sean Rhodes (Code Review) 12 Nov '21

12 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59258 ) Change subject: drivers/intel/gma: Remove _BCL from acpigen ...................................................................... drivers/intel/gma: Remove _BCL from acpigen As `INTEL_GMA_ACPI` is selected by default for most Intel SOC's, but if the brightness control isn't Intels (i.e. `drivers/intel/gma/acpi/default_brightness_levels.asl` isn't included, there wont be a hook for BCL. This results in: ``` No Local Variables are initialized for Method [_BCL] No Arguments are initialized for method [_BCL] ``` Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Icf2f2fa33abd11952c888c9502d1d5ef1ad6544f --- M src/drivers/intel/gma/acpi.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/59258/1 diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index 4a89bb9..5f41079 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -59,17 +59,6 @@ /* ACPI brightness for LCD. */ if (kind == 4) { /* - Method (_BCL, 0, NotSerialized) - { - Return (^^XBCL()) - } - */ - acpigen_write_method("_BCL", 0); - acpigen_emit_byte(RETURN_OP); - acpigen_emit_namestring("^^XBCL"); - acpigen_pop_len(); - - /* Method (_BCM, 1, NotSerialized) { ^^XBCM(Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/59258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf2f2fa33abd11952c888c9502d1d5ef1ad6544f Gerrit-Change-Number: 59258 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021