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Change in coreboot[master]: Documentation/drivers: Add notes on Realtek HW EQ
by Sean Rhodes (Code Review) 12 Nov '21

12 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59263 ) Change subject: Documentation/drivers: Add notes on Realtek HW EQ ...................................................................... Documentation/drivers: Add notes on Realtek HW EQ Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ie13f62622a4cf2b14d36728a8a4a9e3ef24d6852 --- A Documentation/drivers/realtek.md 1 file changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59263/1 diff --git a/Documentation/drivers/realtek.md b/Documentation/drivers/realtek.md new file mode 100644 index 0000000..89cc844 --- /dev/null +++ b/Documentation/drivers/realtek.md @@ -0,0 +1,99 @@ +## Realtek 7-band Hardware Equaliser Configuration + +The Realtek ALC256 and several other codecs support a 7-band hardware +equalizer. The datasheet has extensive documentation on this, as after +it says that it supports it, it provides all the below information on +how to configure it: + +``` + +``` +As this information is extemely helpful, we wrote up the notes below on +how to configure it. Be careful, many, many speakers were hurt, mamed +and even killed during the creation of these notes (particularily setting +the output to 2.5W). + + +The defaults for the HW EQ are below: +``` +0x05350000h < Disable EQ Register +0x05340000h < Dont disable + +0x0535001d < Left Channel +0x05340000 +0x0535001e +0x05340000 + +0x05450000 < Right Channel +0x05440000 +0x0545001d +0x05440000 +0x0545001e +0x05440000 + +0x05350000 < Enable EQ Register +0x05344000 < Dont Enable + +0x02050038 < AGC Settings +0x02044901 +0x02050013 +0x0204292F +0x02050016 +0x02044C50 +``` + +The following settings can be configured: +``` +Settings Default Min Max +AGC Disabled +Threshold: 0dB 0dB -46.5dB +Front Boost: 0dB 0dB 29.25dB +Post Boost: -11.63dB -11.63dB 29.25dB + +High Pass Filter 1 +Mode: Boost Gain Boost Gain 1st order Butterworth +BW: 1000Hz 200Hz 20000Hz +Gain: 0dB -12dB +12dB + +High Pass Filter 2 +Mode: Boost Gain Boost Gain 1st order Butterworth +BW: 1000Hz 200Hz 20000Hz +Gain: 0dB -12dB +12dB + +Low Pass Filter +Mode: Boost Gain Boost Gain 1st order Butterworth +BW: 1000Hz 200Hz 20000Hz +Gain: 0dB -12dB +12dB + +Band Pass Filter 1 +Fc: 3000Hz 1000Hz 20000Hz +BW: 1000Hz 200Hz 10000Hz +Gain: 0dB -12dB +12dB + +Band Pass Filter 2 +Fc: 6000Hz 1000Hz 20000Hz +BW: 1000Hz 200Hz 10000Hz +Gain: 0dB -12dB +12dB + +Band Pass Filter 3 +Fc: 9000Hz 1000Hz 20000Hz +BW: 1000Hz 200Hz 10000Hz +Gain: 0dB -12dB +12dB + +Band Pass Filter 4 +Fc: 9000Hz 1000Hz 20000Hz +BW: 1000Hz 200Hz 10000Hz +Gain: 0dB -12dB +12dB + +Class D Amp +Power: 2.5W 0.25W 2.5W +Resistance: 4ohms 4ohms 8ohms + +EQ Output +Left: 0dB -12dB +12dB +Right: 0dB -12dB +12dB + +VARQ +Q: 0.707 0.1 1 + +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie13f62622a4cf2b14d36728a8a4a9e3ef24d6852 Gerrit-Change-Number: 59263 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5
by Meera Ravindranath (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Maulik V Vaghela, Ravishankar Sarawadi, Tim Wawrzynczak, Reka Norman, Nick Vaccaro, Balaji Manigandan, Raj Astekar, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Ravishankar Sarawadi, Reka Norman, Tim Wawrzynczak, Subrata Banik, Nick Vaccaro, Balaji Manigandan, Raj Astekar, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52731 to look at the new patch set (#9). Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5 ...................................................................... soc/common/smbus: Add support for reading spd data via smbus for DDR5 BUG=b:180458099 TEST=Boot adlrvp DDR5 board to kernel Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/smbuslib.c 2 files changed, 112 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/52731/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/52731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 9 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs
by Kyösti Mälkki (Code Review) 12 Nov '21

12 Nov '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59004 ) Change subject: google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs ...................................................................... google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs Low-level GPIOs should not depend on late cros_gpios that should be guarded with CHROMEOS and implemented for the purpose of ACPI \OIPG package generation. Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59004 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/sarien/chromeos.c 3 files changed, 21 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 3d17a6c..7083c80 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -33,24 +33,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPIO_PCH_WP); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPIO_REC_MODE); } void mainboard_chromeos_acpi_generate(void) @@ -63,11 +53,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -93,7 +78,7 @@ state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 6122b85..726736a 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -31,24 +31,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPP_E15); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPP_E8); } void mainboard_chromeos_acpi_generate(void) @@ -61,11 +51,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -91,7 +76,7 @@ state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 170013a..37fd817a 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -29,24 +29,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPP_E15); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPP_E8); } void mainboard_chromeos_acpi_generate(void) @@ -59,11 +49,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -89,7 +74,7 @@ state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Gerrit-Change-Number: 59004 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google,intel: Add ChromeOS GPIOs to onboard.h
by Kyösti Mälkki (Code Review) 12 Nov '21

12 Nov '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59000 ) Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ...................................................................... mb/google,intel: Add ChromeOS GPIOs to onboard.h Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/chromeos.c A src/mainboard/google/auron/onboard.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/onboard.h M src/mainboard/google/link/chromeos.c M src/mainboard/google/link/onboard.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/onboard.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/onboard.h M src/mainboard/intel/baskingridge/chromeos.c A src/mainboard/intel/baskingridge/onboard.h M src/mainboard/intel/emeraldlake2/chromeos.c A src/mainboard/intel/emeraldlake2/onboard.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/strago/onboard.h 18 files changed, 92 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 3132fd7d..40f98f2 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -7,8 +7,7 @@ #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -/* SPI Write protect is GPIO 16 */ -#define CROS_WP_GPIO 58 +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h new file mode 100644 index 0000000..6d4ff28 --- /dev/null +++ b/src/mainboard/google/auron/onboard.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AURON_ONBOARD_H +#define AURON_ONBOARD_H + +/* SPI Write protect is GPIO 58 */ +#define CROS_WP_GPIO 58 + +#endif diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 2de55b0..2293f93 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -11,9 +11,8 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" +#include "onboard.h" -#define WP_GPIO 6 -#define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index b8da862..f799d04 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -16,4 +16,8 @@ /* 0x00: White LINK LED and Amber ACTIVE LED */ #define BUTTERFLY_NIC_LED_MODE 0x00 + +/* SPI write protect, active low */ +#define WP_GPIO 6 + #endif diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index f4250cc..f77c822 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -6,6 +6,7 @@ #include <southbridge/intel/common/gpio.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -26,12 +27,12 @@ int get_write_protect_state(void) { - return get_gpio(57); + return get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index 7e351e4..efcda92 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -16,4 +16,8 @@ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a #define BOARD_TOUCHSCREEN_IRQ 22 +#define GPIO_REC_MODE 9 + +#define GPIO_SPI_WP 57 + #endif diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 77aa11a..4781f7e 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -8,10 +8,10 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <ec/compal/ene932/ec.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" + +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -20,7 +20,7 @@ struct lb_gpio chromeos_gpios[] = { /* Lid switch GPIO active high (open). */ - {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {GPIO_LID, ACTIVE_HIGH, get_lid_switch(), "lid"}, /* Power Button */ {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, @@ -34,32 +34,27 @@ int get_lid_switch(void) { - return get_gpio(15); + return get_gpio(GPIO_LID); } int get_write_protect_state(void) { - return !get_gpio(70); + return !get_gpio(GPIO_SPI_WP); } int get_recovery_mode_switch(void) { - u8 gpio = !get_gpio(68); - /* GPIO68, active low. For Servo support - * Treat as active high and let the caller invert if needed. */ - printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio); - - return gpio; + return !get_gpio(GPIO_REC_MODE); } static int parrot_ec_running_ro(void) { - return !get_gpio(68); + return get_recovery_mode_switch(); } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index 9bece67..d564c56 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -9,4 +9,13 @@ #define BOARD_TRACKPAD_IRQ_PVT 20 #define BOARD_TRACKPAD_WAKE_GPIO 0x1c +#define GPIO_LID 15 + +/* GPIO68, active low. For Servo support + * Treat as active high and let the caller invert if needed. */ +#define GPIO_REC_MODE 68 + + +#define GPIO_SPI_WP 70 + #endif diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 5453583..0fa78c9 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -6,6 +6,7 @@ #include <southbridge/intel/common/gpio.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -19,12 +20,12 @@ int get_write_protect_state(void) { - return get_gpio(58); + return get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 6b7fdb2..a1f30fd 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -23,4 +23,7 @@ #define PEPPY_BOARD_VERSION_PROTO 0 #define PEPPY_BOARD_VERSION_EVT 1 +/* Write protect is active high */ +#define GPIO_SPI_WP 58 + #endif diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index e68093f..6bbc640 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -12,6 +12,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include <ec/quanta/it8518/ec.h> +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -35,7 +36,7 @@ int get_write_protect_state(void) { - return !get_gpio(7); + return !get_gpio(GPIO_SPI_WP); } int get_lid_switch(void) @@ -77,7 +78,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index a31dffd..2f9b92d 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -11,4 +11,7 @@ #define XHCI_PREBOOT 0 // No PreOS boot support #define XHCI_STREAMS 1 // Sure, lets have streams +/* Write protect is active low */ +#define GPIO_SPI_WP 7 + #endif diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index b6c4164..d4408f4 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -7,12 +7,13 @@ #include <southbridge/intel/common/gpio.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -32,18 +33,18 @@ * Recovery: GPIO69, Connected to J8E3, however the silkscreen says * J8E2. The jump is active high. */ - return get_gpio(69); + return get_gpio(GPIO_REC_MODE); } int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(22); + return !get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h new file mode 100644 index 0000000..66812a5 --- /dev/null +++ b/src/mainboard/intel/baskingridge/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef BASKINGRIDGE_ONBOARD_H +#define BASKINGRIDGE_ONBOARD_H + +/* Recovery: GPIO69, active high - SV_DETECT - J8E3 (silkscreen: J8E2) */ +#define GPIO_REC_MODE 69 + +/* Write protect is active low */ +#define GPIO_SPI_WP 22 + +#endif diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 58732b1..2d0e2e1 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -7,12 +7,13 @@ #include <southbridge/intel/common/gpio.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO22 */ - {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -29,18 +30,18 @@ int get_recovery_mode_switch(void) { /* Recovery: GPIO22, active low */ - return !get_gpio(22); + return !get_gpio(GPIO_REC_MODE); } int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(48); + return !get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h new file mode 100644 index 0000000..658ad83 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef EMERALDLAKE2_ONBOARD_H +#define EMERALDLAKE2_ONBOARD_H + +/* Recovery: GPIO22, active low */ +#define GPIO_REC_MODE 22 + +/* Write protect is active low */ +#define GPIO_SPI_WP 48 + +#endif diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 3f80b68..91ce9ae 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -6,10 +6,7 @@ #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -#define WP_GPIO GP_E_22 - -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index bc2e7a2..d8af569 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -29,6 +29,9 @@ #define JACK_DETECT_GPIO_INDEX 95 /* SCI: Gpio index in N bank */ #define BOARD_SCI_GPIO_INDEX 15 + +#define WP_GPIO GP_E_22 + /* Trackpad: Gpio index in N bank */ #define BOARD_TRACKPAD_GPIO_INDEX 18 -- To view, visit https://review.coreboot.org/c/coreboot/+/59000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Gerrit-Change-Number: 59000 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5
by Meera Ravindranath (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Maulik V Vaghela, Ravishankar Sarawadi, Tim Wawrzynczak, Reka Norman, Nick Vaccaro, Balaji Manigandan, Raj Astekar, Patrick Rudolph, Karthik Ramasubramanian. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52731 ) Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5 ...................................................................... Patch Set 8: (3 comments) File src/include/spd_bin.h: https://review.coreboot.org/c/coreboot/+/52731/comment/e38e7915_722cc9cf PS7, Line 42: > nit: extra space Done File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/52731/comment/4eda481d_7e0f34e7 PS7, Line 55: > Can we add a comment here about the hub addressing, e,g. […] Done https://review.coreboot.org/c/coreboot/+/52731/comment/49bc2cd6_cb99f992 PS7, Line 100: const struct spd_offset_table *tbl; : const struct spd_offset_table *table_select; : u32 byte; : u32 stop; : u8 page; : : page = (u8) (~0); : table_select = (struct spd_offset_table *)spd_ddr5_table; : stop = ARRAY_SIZE(spd_ddr5_table) > I think these make more sense declared in the `is_spd5_hub` if scope as they are specific to that ca […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 11:14:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5
by Meera Ravindranath (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Maulik V Vaghela, Ravishankar Sarawadi, Tim Wawrzynczak, Reka Norman, Meera Ravindranath, Nick Vaccaro, Balaji Manigandan, Raj Astekar, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Ravishankar Sarawadi, Reka Norman, Tim Wawrzynczak, Subrata Banik, Nick Vaccaro, Balaji Manigandan, Raj Astekar, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52731 to look at the new patch set (#8). Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5 ...................................................................... soc/common/smbus: Add support for reading spd data via smbus for DDR5 BUG=b:180458099 TEST=Boot adlrvp DDR5 board to kernel Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/smbuslib.c 2 files changed, 109 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/52731/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add set batteryinfo support
by Sumeet R Pawnikar (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59262 ) Change subject: soc/intel/alderlake: Add set batteryinfo support ...................................................................... soc/intel/alderlake: Add set batteryinfo support Add set batteryinfo support under acpi for Alder Lake. BUG=b:206057712 BRANCH=None TEST=Build and test on brya system Change-Id: I02350a2c8e3dd4cdb061a6976f44e4b839a305a4 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/alderlake/acpi.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59262/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 0fb989d..0096505 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -9,6 +9,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> @@ -283,6 +284,9 @@ /* Get the powerinfo config details */ ret = google_chromeec_get_powerinfo_config(); + + /* Set the batteryinfo config details */ + google_chromeec_set_batteryinfo_config(ISL9241_BC12_MIN_VOLTAGE); } int soc_madt_sci_irq_polarity(int sci) -- To view, visit https://review.coreboot.org/c/coreboot/+/59262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02350a2c8e3dd4cdb061a6976f44e4b839a305a4 Gerrit-Change-Number: 59262 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: add battery participant support
by Sumeet R Pawnikar (Code Review) 12 Nov '21

12 Nov '21

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59261 ) Change subject: ec/google/chromeec: add battery participant support ...................................................................... ec/google/chromeec: add battery participant support Add battery participant support BUG=b:206057712 BRANCH=None TEST=Build and test battery info Change-Id: I2781ceff611877aef37141f195f21f9bdc31eb4c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/59261/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 4477d9e..ca42291 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1862,3 +1862,25 @@ return 0; } + +int google_chromeec_set_batteryinfo_config(uint32_t uvth) +{ + struct ec_battery_info_v1 params = { + .uvth_value = uvth + }; + + struct chromeec_command cmd = { + .cmd_code = EC_CMD_BATTERY_INFO, + .cmd_version = 1, + .cmd_size_in = sizeof(params), + .cmd_data_in = &params, + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 56fca2e..6406ff0 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -415,6 +415,13 @@ */ int google_chromeec_get_powerinfo_config(void); +/** + * Send battery config details to EC + * @param resp Filled with host command protocol information + * @return 0 on success, -1 on error + */ +int google_chromeec_set_batteryinfo_config(uint32_t uvth); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4637d1c..d1af590 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -4706,6 +4706,24 @@ } __ec_align2; /*****************************************************************************/ +/* Battery info. */ + +/* Default low voltage thershold value */ +#define ISL9241_BC12_MIN_VOLTAGE 4096 + +/* + * Get battery info. + * + * Note: v0 of this command is deprecated + */ +#define EC_CMD_BATTERY_INFO 0x00A5 + +struct ec_battery_info_v1 { + uint32_t uvth_value; +} __ec_align1; + + +/*****************************************************************************/ /* Hibernate/Deep Sleep Commands */ /* Set the delay before going into hibernation. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2781ceff611877aef37141f195f21f9bdc31eb4c Gerrit-Change-Number: 59261 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEV...
by Varshit B Pandya (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59260 to look at the new patch set (#2). Change subject: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD ...................................................................... mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:199823938 TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED during boot. Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/59260/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Gerrit-Change-Number: 59260 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
by Meera Ravindranath (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Angel Pons, Subrata Banik, Nick Vaccaro, Ronak Kanabar, Patrick Rudolph. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 ) Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64 ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52730/comment/b47200d8_8d40a557 PS5, Line 7: mb/intel/adlrvp: Configure DIMM_MAX > Maybe: […] Ack https://review.coreboot.org/c/coreboot/+/52730/comment/908cdf5b_373d2df4 PS5, Line 9: Adlrvp DDR5 board has 8 DIMM slots(4 channels and 2 DIMMs : per channel) > Please: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52730 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 11:03:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021