coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/redrix: Correct WWAN power sequence
by Chen Wisley (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59267 to review the following change. Change subject: mb/google/brya/var/redrix: Correct WWAN power sequence ...................................................................... mb/google/brya/var/redrix: Correct WWAN power sequence Correct the WWAN power sequence to meet spec BUG=b:206079177 TEST=build Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix/include/variant/gpio.h 3 files changed, 31 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59267/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 8d58fa5..a20cc9a 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -42,6 +42,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_GFX_GENERIC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_KANO bool "-> Kano" diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index f35e0fd..f8e0000 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -37,13 +37,14 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : DDP2_CTRLCLK ==> NC */ PAD_NC(GPP_E20, NONE), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), - /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), @@ -67,11 +68,14 @@ PAD_NC(GPP_S6, NONE), /* S7 : SNDW3_DATA ==> NC */ PAD_NC(GPP_S7, NONE), - + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ @@ -91,16 +95,18 @@ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> NC */ - PAD_NC(GPP_E0, NONE), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L */ + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ @@ -115,6 +121,13 @@ PAD_CFG_GPO(GPP_B4, 0, DEEP), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -126,3 +139,9 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h index c4fe342..99d09b2 100644 --- a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h @@ -5,4 +5,10 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Gerrit-Change-Number: 59267 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01
by Tim Wawrzynczak (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Ronak Kanabar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59013 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Since this is just opening up a UPD, there is no structure size or offset changes, so no cq-depend is necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/59013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Gerrit-Change-Number: 59013 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:30:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/chromeos: Update extract_blobs script
by Matt DeVillier (Code Review) 12 Nov '21

12 Nov '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59266 ) Change subject: util/chromeos: Update extract_blobs script ...................................................................... util/chromeos: Update extract_blobs script - Handle older CrOS firmware which lacks a COREBOOT FMAP region - Add support for all blobs used in CrOS firmware 2013 to current - Put extracted blobs in their own directory Change-Id: Idaa39eca3be68a9327cead9b21c35a6c7a3a8166 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/chromeos/extract_blobs.sh 1 file changed, 91 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59266/1 diff --git a/util/chromeos/extract_blobs.sh b/util/chromeos/extract_blobs.sh index 39f2a3b..eee7785 100755 --- a/util/chromeos/extract_blobs.sh +++ b/util/chromeos/extract_blobs.sh @@ -2,40 +2,106 @@ # # SPDX-License-Identifier: GPL-2.0-only -set -x +if [ ! -f "$1" ] ; then + echo "Error: You must provide a valid filename" + exit 1 +fi IMAGE=$1 +DIR=$(basename $IMAGE) +DIR="${DIR%.*}-blobs" +mkdir -p $DIR -if [ ! -r "$IMAGE" ]; then - echo "Can't find image $IMAGE." - exit 1 +if [ -f ./cbfstool ]; then + CBFSTOOL="./cbfstool" +else + CBFSTOOL=$(which cbfstool) +fi +if [[ "$CBFSTOOL" = "" ]]; then + echo "Error: cbfstool must be in your path or exist locally" + exit 1 fi -CBFSTOOL=$(which cbfstool) -if [ $? != 0 ]; then - echo "Can't find cbfstool." - exit 1 +if [ -f ./ifdtool ]; then + IFDTOOL="./ifdtool" +else + IFDTOOL=$(which ifdtool) +fi +if [[ "$IFDTOOL" = "" ]]; then + echo "Error: ifdtool must be in your path or exist locally" + exit 1 fi -IFDTOOL=$(which ifdtool) -if [ $? != 0 ]; then - echo "Can't find ifdtool." - exit 1 +# ensure valid coreboot image / get list of main COREBOOT CBFS contents +REGION="" +if ! $CBFSTOOL $IMAGE print > $DIR/cbfs.txt 2>/dev/null ; then + # try using BOOT_STUB region + if ! $CBFSTOOL $IMAGE print -r BOOT_STUB > $DIR/cbfs.txt ; then + echo "Error reading CBFS: $IMAGE is not a valid coreboot image" + exit 1 + else + REGION="-r BOOT_STUB" + fi fi -$CBFSTOOL $IMAGE print +echo "" +echo "Extracting blobs..." +echo "" -if [ $? -ne 0 ]; then - echo "Not a coreboot image: $IMAGE" - exit 1 +# extract flash regions +if ! $IFDTOOL -x $IMAGE >/dev/null ; then + echo "Error reading flash descriptor/extracting flash regions" + exit 1 fi - -PCI=$($CBFSTOOL $IMAGE print|grep pci|cut -f1 -d\ ) -MRC=$($CBFSTOOL $IMAGE print|grep mrc.bin|cut -f1 -d\ ) - -$CBFSTOOL $IMAGE extract -n $PCI -f $PCI -$CBFSTOOL $IMAGE extract -n $MRC -f $MRC -$IFDTOOL -x $IMAGE -mv flashregion_0_flashdescriptor.bin flashdescriptor.bin -mv flashregion_2_intel_me.bin me.bin +# rename to normal convention; drop unused regions +mv flashregion_0_flashdescriptor.bin $DIR/flashdescriptor.bin +mv flashregion_2_intel_me.bin $DIR/me.bin rm flashregion_*.bin + +# extract microcode +$CBFSTOOL $IMAGE extract $REGION -n cpu_microcode_blob.bin -f $DIR/cpu_microcode_blob.bin + +# extract VGA BIOS +VGA=$(cat $DIR/cbfs.txt | grep pci | cut -f1 -d\ ) +if [ "$VGA" != "" ]; then + $CBFSTOOL $IMAGE extract $REGION -n $VGA -f $DIR/vgabios.bin +fi + +# extract MRC.bin +MRC=$(cat $DIR/cbfs.txt | grep mrc.bin | cut -f1 -d\ ) +if [ "$MRC" != "" ]; then + $CBFSTOOL $IMAGE extract $REGION -n $MRC -f $DIR/$MRC +fi + +# extract refcode +REF=$(cat $DIR/cbfs.txt | grep refcode | cut -f1 -d\ ) +if [ "$REF" != "" ]; then + $CBFSTOOL $IMAGE extract $REGION -n fallback/refcode -f $DIR/refcode.elf -m x86 +fi + +# extract FSP blobs +for FSP in $(cat $DIR/cbfs.txt | grep fsp | cut -f1 -d\ ); +do $CBFSTOOL $IMAGE extract $REGION -n $FSP -f $DIR/$FSP; +done + +# extract audio blobs +for AUD in $(cat $DIR/cbfs.txt | grep -e "-2ch-" -e "-4ch-" | cut -f1 -d\ ); +do $CBFSTOOL $IMAGE extract $REGION -n $AUD -f $DIR/$AUD; +done + +# extract VBTs +for VBT in $(cat $DIR/cbfs.txt | grep vbt | cut -f1 -d\ ); +do $CBFSTOOL $IMAGE extract $REGION -n $VBT -f $DIR/$VBT; +done + +# extract IFWI +IFWI=$(cbfstool $IMAGE layout -w | grep IFWI) +if [ "$IFWI" != "" ]; then + $CBFSTOOL $IMAGE read -r IFWI -f $DIR/ifwi.bin +fi + +# a little housekeeping +rm $DIR/cbfs.txt + +echo "" +echo "All done" -- To view, visit https://review.coreboot.org/c/coreboot/+/59266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaa39eca3be68a9327cead9b21c35a6c7a3a8166 Gerrit-Change-Number: 59266 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons
by Felix Singer (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Abhijeet Rao, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 ) Change subject: soc/intel/alderlake: Disable VT-d for early silicons ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Gerrit-Change-Number: 59191 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:13:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: utils: Add initial version of "remove_unused_code" script
by Raul Rangel (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Martin Roth, Piotr Król. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59169 ) Change subject: utils: Add initial version of "remove_unused_code" script ...................................................................... Patch Set 1: (28 comments) Patchset: PS1: > Raul, When you have the time, could you do a review of the bash? Sure :) File util/scripts/rm_unused_code: https://review.coreboot.org/c/coreboot/+/59169/comment/1cce47bc_7cef8db8 PS1, Line 35: show_version() { : echo : _echo_color "${BOLD}${GREEN}" "${PROGNAME} version ${VERSION}" 1 : echo : } nit: I would move this under _echo_color https://review.coreboot.org/c/coreboot/+/59169/comment/4e50b860_4967b6be PS1, Line 41: _echo_color Can you add a comment describing the args. https://review.coreboot.org/c/coreboot/+/59169/comment/331db0f0_27dcf2ca PS1, Line 50: test -n "${VERBOSE}" You have `-e set above. Won't this cause the script to bail if this is evaluates to false? I think you need to use an `if [[ -n "${VERBOSE}" ]]; https://review.coreboot.org/c/coreboot/+/59169/comment/3ea9f649_701938db PS1, Line 55: ( Why the subshell? https://review.coreboot.org/c/coreboot/+/59169/comment/6f1d17be_45b97c3f PS1, Line 55: >&2 Shouldn't this go at the end? https://review.coreboot.org/c/coreboot/+/59169/comment/97fd0737_6f88dafb PS1, Line 59: $(getopt -l version,help,debug,nocolor,blddir: -o b:DhV -- "$@") I never remember, do we need to quote this? https://review.coreboot.org/c/coreboot/+/59169/comment/413e4f00_3cf75c97 PS1, Line 60: getopt_ret=$? Since you have -e, I think the script will bail when the line above fails. https://review.coreboot.org/c/coreboot/+/59169/comment/7991fa75_af1152a2 PS1, Line 72: BLD_DIR Do you need to `shift` after pulling the arg off? https://review.coreboot.org/c/coreboot/+/59169/comment/a04f1e3a_9e6ec9ce PS1, Line 115: ${dir} quote https://review.coreboot.org/c/coreboot/+/59169/comment/06479c7e_cc999de8 PS1, Line 120: find "${dir}" -depth -type d -exec /bin/bash -c \ : 'if echo "$1" | grep -q "$2"; then exit; fi && : if [[ "$(cd "$1" && find . -maxdepth 1 | grep -v "./Makefile")" = "." ]]; then : rm -rf "$1"; fi' shell {} \ : ${REQUIRED_MAKEFILES} \; Could you invert this? while read -r FILE; do ... Do processing on each file done < <(find "${dir}" -depth -type d) https://review.coreboot.org/c/coreboot/+/59169/comment/dce6629f_f416daf2 PS1, Line 125: ${dir} "" https://review.coreboot.org/c/coreboot/+/59169/comment/8980931b_4d771ca0 PS1, Line 189: { You could replace the {} these with () to make the function invoke the subshell. https://review.coreboot.org/c/coreboot/+/59169/comment/5ba92ec7_93fd3fc1 PS1, Line 196: # find "${BLD_DIR}" -type f -exec touch -a --date="2020-01-01 00:00:00" {} \; ? https://review.coreboot.org/c/coreboot/+/59169/comment/5c237e9c_ecf0f87b PS1, Line 205: KEEP_FILES Can you declare KEEP_FILES as an array above,then use "${KEEP_FILES[@]}" https://review.coreboot.org/c/coreboot/+/59169/comment/76c0bfac_58ba65c0 PS1, Line 206: find Why do we need the find? Can this be replaced with `touch "${BLD_DIR}/${file}"`? https://review.coreboot.org/c/coreboot/+/59169/comment/bd663892_919836f1 PS1, Line 211: $1 "" https://review.coreboot.org/c/coreboot/+/59169/comment/1935f8cf_d251c6d7 PS1, Line 214: ${CONFIG_FILE} "" https://review.coreboot.org/c/coreboot/+/59169/comment/604290d3_5408b95a PS1, Line 221: || exit 1 Your `-e` should take care this, but it doesn't hurt. https://review.coreboot.org/c/coreboot/+/59169/comment/fb59d18d_ce9f8f3e PS1, Line 228: I think you can add a `-path ./.git -prune` to the find command and avoid the grep. https://review.coreboot.org/c/coreboot/+/59169/comment/2fb51a67_41177700 PS1, Line 228: MODIFIED_FILES Could use `readarray MODIFIED_FILES < <(find ...)` https://review.coreboot.org/c/coreboot/+/59169/comment/8a6350e6_fdf2700e PS1, Line 229: (echo "${MODIFIED_FILES}" | wc -l) If you use an array you can use "${#MODIFIED_FILES[@]}" https://review.coreboot.org/c/coreboot/+/59169/comment/0651a1f3_83b0f3e0 PS1, Line 236: -exec rm {} \; -delete https://review.coreboot.org/c/coreboot/+/59169/comment/d4f96c21_48dfeeb3 PS1, Line 249: CLEAN_DIR_LIST I would make it an array: "${CLEAN_DIR_LIST[@]}" https://review.coreboot.org/c/coreboot/+/59169/comment/17fc0576_a74cbbb2 PS1, Line 252: -exec rm {} \; -delete https://review.coreboot.org/c/coreboot/+/59169/comment/86f8e177_56588ae7 PS1, Line 264: && Shouldn't need the && with `-e` https://review.coreboot.org/c/coreboot/+/59169/comment/f69219c2_36335847 PS1, Line 279: ${HASH} "" https://review.coreboot.org/c/coreboot/+/59169/comment/eea9553d_7c890aa8 PS1, Line 285: ${HASH} "" -- To view, visit https://review.coreboot.org/c/coreboot/+/59169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4 Gerrit-Change-Number: 59169 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:08:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: change help text of FLASH_DUAL_READ
by Felix Held (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen, Rex-BC Chen. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59244 ) Change subject: soc/mediatek: change help text of FLASH_DUAL_READ ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b81cdeba3b693451f66e003fb470c9f8c19ad9 Gerrit-Change-Number: 59244 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 15:22:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by Paul Fagerburg (Code Review) 12 Nov '21

12 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58969 ) Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... soc/mediatek/mt8195: Add APU device apc driver Add APU device apc driver and set up permissions. APU has its own device apc for control access by domains. For Domain 0, the access to the following slaves are restricted to security read and write: apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser, apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4 apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4 For VPU, D0/D5 are set as no protection, other domains are forbidden. For other slaves, the D0 is no protection, other domains are forbidden. BUG=b:203145462 BRANCH=cherry TEST=boot cherry, check dump log and test permissions Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58969 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc.h 5 files changed, 330 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved flora.fu(a)mediatek.com: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index c362899..53883b4 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -23,6 +23,7 @@ verstage-y += ../common/wdt.c wdt.c ramstage-y += apusys.c +ramstage-y += apusys_devapc.c romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c new file mode 100644 index 0000000..cecbe47 --- /dev/null +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/apusys_devapc.h> +#include <soc/devapc.h> + +static const enum domain_id domain_map[] = { + DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3, DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7, + DOMAIN_8, DOMAIN_9, DOMAIN_10, DOMAIN_11, DOMAIN_12, DOMAIN_13, DOMAIN_14, DOMAIN_15, +}; + +#define DAPC_APU_AO_SYS0_ATTR(...) \ + { \ + { \ + DAPC_PERM_ATTR_16(__VA_ARGS__) \ + } \ + } +#define DAPC_APU_NOC_AO_SYS0_ATTR(...) \ + { \ + { \ + DAPC_PERM_ATTR_16(__VA_ARGS__) \ + } \ + } + +/* NOC DAPC */ +static const struct apc_apu_dom_16 apusys_noc_dapc[] = { + /* 0 */ + DAPC_APU_NOC_AO_SYS0_ATTR("slv00-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv00-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv00-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv01-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv01-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv01-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-3", NO_PROTECTION, FORBIDDEN15), + + /* 10 */ + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-4", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-3", NO_PROTECTION, FORBIDDEN15), +}; +_Static_assert(ARRAY_SIZE(apusys_noc_dapc) == APUSYS_NOC_DAPC_AO_SLAVE_NUM); + +/* AO DAPC */ +static const struct apc_apu_dom_16 apusys_ao_apc[] = { + /* 0 */ + DAPC_APU_AO_SYS0_ATTR("apusys_ao-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-2", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-4", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-5", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-6", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-8", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-9", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("md32_apb_s-0", NO_PROTECTION, FORBIDDEN15), + + /* 10 */ + DAPC_APU_AO_SYS0_ATTR("md32_apb_s-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("md32_apb_s-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("md32_debug_apb", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_con2_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_con1_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sctrl_reviscer", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sema_stimer", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_emi_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_edma0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_edma1", NO_PROTECTION, FORBIDDEN15), + + /* 20 */ + DAPC_APU_AO_SYS0_ATTR("apu_cpe_sensor", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_cpe_coef", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_cpe_ctrl", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sensor_wrp_dla_0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sensor_wrp_dla_1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_dapc_ao", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_dapc", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("infra_bcrm", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("infra_ao_bcrm", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("noc_dapc", NO_PROTECTION, FORBIDDEN15), + + /* 30 */ + DAPC_APU_AO_SYS0_ATTR("apu_noc_bcrm", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_noc_config_0", NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN12), + DAPC_APU_AO_SYS0_ATTR("apu_noc_config_1", NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN12), + DAPC_APU_AO_SYS0_ATTR("apu_noc_config_2", NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN12), + DAPC_APU_AO_SYS0_ATTR("vpu_core0_config-0", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("vpu_core0_config-1", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("vpu_core1_config-0", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("vpu_core1_config-1", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-1", NO_PROTECTION, FORBIDDEN15), + + /* 40 */ + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r1", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r2", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r3", SEC_RW_ONLY, FORBIDDEN15), + + /* 50 */ + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r4", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r1", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r2", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r3", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r4", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_rsi2_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_s0_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_n0_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_acp_ssc_config", NO_PROTECTION, FORBIDDEN15), + + /* 60 */ + DAPC_APU_AO_SYS0_ATTR("apu_s1_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_n1_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-4", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-5", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("vpu_core0_debug_apb", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("vpu_core1_debug_apb", NO_PROTECTION, FORBIDDEN15), + + /* 70 */ + DAPC_APU_AO_SYS0_ATTR("apb_infra_dbg_ctl", NO_PROTECTION, FORBIDDEN15), +}; +_Static_assert(ARRAY_SIZE(apusys_ao_apc) == APUSYS_APC_SYS0_AO_SLAVE_NUM); + +static int set_slave_noc_dapc(u32 slave, enum domain_id domain_id, enum devapc_perm_type perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base; + + if (perm >= PERM_NUM || perm < 0) { + printk(BIOS_ERR, "[NOC_DAPC] permission type:%#x is not supported!\n", perm); + return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + } + + if (slave >= APUSYS_NOC_DAPC_AO_SLAVE_NUM || domain_id >= APUSYS_NOC_DAPC_AO_DOM_NUM) { + printk(BIOS_ERR, "[NOC_DAPC] %s: %s, %s:%#x, %s:%#x\n", __func__, + "out of boundary", "slave", slave, "domain_id", domain_id); + return APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + + apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + base = (void *)((size_t)APUSYS_NOC_DAPC_AO_BASE + domain_id * 0x40 + + apc_register_index * 4); + clrsetbits32(base, 0x3U << (apc_set_index * 2), perm << (apc_set_index * 2)); + + return APUSYS_APC_OK; +} + +static void dump_apusys_noc_dapc(void) +{ + u32 reg_num; + size_t d, i; + + reg_num = DIV_ROUND_UP(ARRAY_SIZE(apusys_noc_dapc), + APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM); + for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { + for (i = 0U; i < reg_num; i++) + printk(BIOS_DEBUG, "[NOCDAPC] D%ld_APC_%ld: %#x\n", d, i, + read32((void *)(APUSYS_NOC_DAPC_AO_BASE + d * 0x40 + i * 4))); + } + printk(BIOS_DEBUG, "[NOCDAPC] APC_CON: %#x\n", read32(APUSYS_NOC_DAPC_CON)); +} + +static int set_slave_apc(u32 slave, enum domain_id domain_id, enum devapc_perm_type perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base; + + if (perm >= PERM_NUM || perm < 0) { + printk(BIOS_ERR, "[APUAPC] perm type:%#x is not supported!\n", perm); + return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + } + + if (slave >= APUSYS_APC_SYS0_AO_SLAVE_NUM || domain_id >= APUSYS_APC_SYS0_AO_DOM_NUM) { + printk(BIOS_ERR, "[APUAPC] %s: %s, %s:%#x, %s:%#x\n", __func__, + "out of boundary", "slave", slave, "domain_id", domain_id); + return APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + + apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + base = (void *)((size_t)APUSYS_APC_AO_BASE + domain_id * 0x40 + apc_register_index * 4); + + clrsetbits32(base, 0x3U << (apc_set_index * 2), perm << (apc_set_index * 2)); + + return APUSYS_APC_OK; +} + +static void dump_apusys_ao_apc(void) +{ + u32 reg_num; + size_t d, i; + + reg_num = + DIV_ROUND_UP(ARRAY_SIZE(apusys_ao_apc), APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM); + for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { + for (i = 0U; i < reg_num; i++) + printk(BIOS_DEBUG, "[APUAPC] D%ld_APC_%ld: %#x\n", d, i, + read32((void *)(APUSYS_APC_AO_BASE + d * 0x40 + i * 4))); + } + printk(BIOS_DEBUG, "[APUAPC] APC_CON: %#x\n", read32(APUSYS_APC_CON)); +} + +static int set_apusys_noc_dapc(void) +{ + int ret = APUSYS_APC_OK; + size_t i, j; + + for (i = 0; i < ARRAY_SIZE(apusys_noc_dapc); i++) { + for (j = 0; j < ARRAY_SIZE(apusys_noc_dapc[i].d_permission); j++) { + ret = set_slave_noc_dapc(i, j, apusys_noc_dapc[i].d_permission[j]); + if (ret) + printk(BIOS_ERR, "[APUAPC] fail (%ld, %ld)(%d)!\n", i, j, ret); + } + } + + return ret; +} + +static int32_t set_apusys_ao_apc(void) +{ + int ret = APUSYS_APC_OK; + size_t i, j; + + for (i = 0; i < ARRAY_SIZE(apusys_ao_apc); i++) { + for (j = 0; j < ARRAY_SIZE(apusys_ao_apc[j].d_permission); j++) { + ret = set_slave_apc(i, domain_map[j], apusys_ao_apc[i].d_permission[j]); + if (ret) + printk(BIOS_ERR, "[APUAPC] fail (%ld, %ld)(%d)!\n", i, j, ret); + } + } + + return ret; +} + +void start_apusys_devapc(void) +{ + int ret = APUSYS_APC_OK; + + /* Check violation status */ + printk(BIOS_DEBUG, "[APUAPC] vio %d\n", read32(APUSYS_APC_CON) & 0x80000000); + + /* Initial Permission */ + ret = set_apusys_ao_apc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_ao_apc", + ret ? "FAILED" : "SUCCESS"); + + /* Lock */ + write32(APUSYS_SYS0_APC_LOCK_0, APU_SCTRL_REVISER | DEVAPC_AO_WRAPPER); + + /* Initial NoC Permission */ + ret = set_apusys_noc_dapc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_noc_dapc", + ret ? "FAILED" : "SUCCESS"); + + dump_apusys_ao_apc(); + dump_apusys_noc_dapc(); + + printk(BIOS_DEBUG, "[APUAPC] %s done\n", __func__); +} diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index 9354353..c41b1ac 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <soc/devapc.h> +#include <soc/apusys_devapc.h> static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { /* 0 */ @@ -1884,4 +1885,7 @@ if (devapc_init[i].dump) devapc_init[i].dump(devapc_ao_base); } + + /* Set up APUSYS Permission */ + start_apusys_devapc(); } diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index cbe704c..d9486b3 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -81,6 +81,8 @@ IOCFG_TL_BASE = IO_PHYS + 0x01F40000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, APU_MBOX_BASE = IO_PHYS + 0x09000000, + APUSYS_APC_AO_BASE = IO_PHYS + 0x090F8000, + APUSYS_NOC_DAPC_AO_BASE = IO_PHYS + 0x090FC000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, diff --git a/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h new file mode 100644 index 0000000..4b9e75f --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef APUSYS_DEVAPC_H +#define APUSYS_DEVAPC_H + +enum apusys_apc_error { + APUSYS_APC_OK = 0, + APUSYS_APC_ERR_GENERIC, + APUSYS_APC_ERR_INVALID_CMD, + APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED, + APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED, + APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED, + APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED, + APUSYS_APC_ERR_OUT_OF_BOUNDARY, + APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED, +}; + +struct apc_apu_dom_16 { + unsigned char d_permission[16]; +}; + +#define APUSYS_APC_CON ((void *)(APUSYS_APC_AO_BASE + 0x00F00)) +#define APUSYS_SYS0_APC_LOCK_0 ((void *)(APUSYS_APC_AO_BASE + 0x00700)) +#define APUSYS_NOC_DAPC_CON ((void *)(APUSYS_NOC_DAPC_AO_BASE + 0x00F00)) + +#define APU_SCTRL_REVISER BIT(15) +#define DEVAPC_AO_WRAPPER BIT(8) + +#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_APC_SYS0_AO_DOM_NUM 16U +#define APUSYS_APC_SYS0_AO_SLAVE_NUM 71U + +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 15U + +void start_apusys_devapc(void); + +#endif /* APUSYS_DEVAPC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 10 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/cezanne: Use LZ4 for FSP-S
by Paul Fagerburg (Code Review) 12 Nov '21

12 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59026 ) Change subject: soc/amd/cezanne: Use LZ4 for FSP-S ...................................................................... soc/amd/cezanne: Use LZ4 for FSP-S This change increases the fsps.bin by 20 KiB, but it decreases decompression time. When not using preloading we save about 4 ms, when using preloading we save about 6. BUG=b:179699789 TEST=Boot nipperkin to OS fsps.bin 0x4afc0 fsp 66253 LZMA (200704 decompressed) fsps.bin 0x45fc0 fsp 87157 LZ4 (200704 decompressed) - FSP-S / no async - | 505 - starting to verify keyblock/preamble (RSA) | 9.36 | 11.012 Δ( 1.65, 0.11%) | ... | 971 - loading FSP-S | 7.095 | 6.141 Δ( -0.95, -0.07%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.008 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 15.149 | 8.98 Δ( -6.17, -0.42%) | | 954 - calling FspSiliconInit | 0.038 | 0.037 Δ( -0.00, -0.00%) | - FSP-S / async - | 508 - finished loading body | 177.978 | 179.689 Δ( 1.71, 0.12%) | ... | 971 - loading FSP-S | 6.928 | 7.225 Δ( 0.30, 0.02%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.011 | 0.01 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 8.312 | 0.241 Δ( -8.07, -0.58%) | | 954 - calling FspSiliconInit | 0.091 | 0.09 Δ( -0.00, -0.00%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59026 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 16f1d3f..aaa3811 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -21,7 +21,7 @@ select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA - select FSP_COMPRESS_FSP_S_LZMA + select FSP_COMPRESS_FSP_S_LZ4 select GENERIC_GPIO_LIB select HAVE_ACPI_TABLES select HAVE_CF9_RESET -- To view, visit https://review.coreboot.org/c/coreboot/+/59026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Gerrit-Change-Number: 59026 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Preload FSP-S
by Paul Fagerburg (Code Review) 12 Nov '21

12 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59025 ) Change subject: soc/amd/cezanne: Preload FSP-S ...................................................................... soc/amd/cezanne: Preload FSP-S FSP-S is normally memmapped and then decompressed. There are about 7 ms between starting ramstage, and loading FSP-S. By preloading we can ensure the fsps.bin is already in RAM by the time we need it. This reduces boot time by about 7 ms. BUG=b: TEST=Boot nipperkin and see ~7ms reduction in boot time | 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) | | 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) | | 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) | | 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) | | 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) | | 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) | CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1) CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208 waiting for thread took 1 us <-- fsps.bin was preloaded CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/preload.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 8db0f6c..58df740 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += graphics.c ramstage-y += i2c.c ramstage-y += mca.c +ramstage-y += preload.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c new file mode 100644 index 0000000..d8b0891 --- /dev/null +++ b/src/soc/amd/cezanne/preload.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <fsp/api.h> + +static void start_fsps_preload(void *unused) +{ + preload_fsps(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95 Gerrit-Change-Number: 59025 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA
by Paul Fagerburg (Code Review) 12 Nov '21

12 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59130 ) Change subject: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA ...................................................................... soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA This will enable reading FSP-S/M using the SPI DMA controller. BUG=B:179699789 TEST=Build guybrush with SPI DMA enabled and verify alignment is set Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59130 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/block/lpc/Kconfig 1 file changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index 76f4ec7..6419269 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -16,12 +16,20 @@ help Select this option to enable SPI DMA support. -# The LPC SPI DMA controller requires the destination buffers to be 64 byte +# The LPC SPI DMA controller requires the source and destination to be 64 byte # aligned. config CBFS_CACHE_ALIGN int default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA +config FSP_ALIGNMENT_FSP_S + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + +config FSP_ALIGNMENT_FSP_M + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/59130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Gerrit-Change-Number: 59130 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2021