coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya: Create vell variant
by Tim Wawrzynczak (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Kevin Chiu, Wisley Chen, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59242 ) Change subject: mb/google/brya: Create vell variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c Gerrit-Change-Number: 59242 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:59:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: De-assert SSD PERST# in romstage
by Chen Wisley (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59269 to review the following change. Change subject: mb/google/brya/var/redrix: De-assert SSD PERST# in romstage ...................................................................... mb/google/brya/var/redrix: De-assert SSD PERST# in romstage After CB:57539 applied, it can support romstage GPIO table override. We can move SSD PERST# de-assertion to romstage. BUG=b:199714453 TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8 --- M src/mainboard/google/brya/variants/redrix/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59269/1 diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index 6182ec2..5fd26d4 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -113,7 +113,7 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and - * then deassert PERST# in ramstage + * then deassert PERST# in romstage */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), @@ -122,6 +122,8 @@ }; static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8 Gerrit-Change-Number: 59269 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Felix Held (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58871 ) Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > I have not tested on Stoeyridge. But I assume it doesn't break the board. […] will it be sufficient to see if i get serial console output on a stoneyridge chromebook? i can try that and that will show that the x86 part still starts; if i need to boot into chromeos that would be more difficult -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:50:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01
by Tim Wawrzynczak (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Ronak Kanabar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59013 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Since this is just opening up a UPD, there is no structure size or offset changes, so no cq-depend i […] Verified by cherry-picking this on top of current FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/59013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Gerrit-Change-Number: 59013 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:48:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs
by Paul Fagerburg (Code Review) 12 Nov '21

12 Nov '21

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59081 ) Change subject: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs ...................................................................... soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs List of changes: 1. Add PEG60/10/62 IDs (0x464d/0x460d/0x463d) into device/pci_ids.h 2. Add these new IDs into pcie_device_ids[] in pcie.c BUG=b:205668996 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59081 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/pcie/pcie.c 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Kane Chen: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1ed6ac9..c6ef121 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3332,6 +3332,10 @@ #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6 0x4b3d #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7 0x4b3e +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP1 0x464d +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP2 0x460d +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP3 0x463d + #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1 0x51b8 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2 0x51b9 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3 0x51ba diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 6d3d6ab..0c3e225 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -313,6 +313,9 @@ PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP3, PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1, PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2, PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3, -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 3 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge/include/pci_devs: remove unused DEVID defines
by Felix Held (Code Review) 12 Nov '21

12 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59268 ) Change subject: soc/amd/stoneyridge/include/pci_devs: remove unused DEVID defines ...................................................................... soc/amd/stoneyridge/include/pci_devs: remove unused DEVID defines None of the *_DEVID defines was used in the code, so drop those. The SoC code uses the PCI ID defines from include/device/pci_ids.h instead. Since it might still be useful to have the PCI device IDs as a reference in the SoC's pci_devs.h, add those as comments instead. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b --- M src/soc/amd/stoneyridge/include/soc/pci_devs.h 1 file changed, 21 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/59268/1 diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 6af657f..4e5c8fc 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -6,17 +6,15 @@ #include <device/pci_def.h> #include <amdblocks/pci_devs.h> -/* GNB Root Complex */ +/* GNB Root Complex: GNB_DEVID 0x1576 */ #define GNB_DEV 0x0 #define GNB_FUNC 0 -#define GNB_DEVID 0x1576 #define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) #define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) -/* IOMMU */ +/* IOMMU: IOMMU_DEVID 0x1577 */ #define IOMMU_DEV 0x0 #define IOMMU_FUNC 2 -#define IOMMU_DEVID 0x1577 #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) @@ -41,59 +39,51 @@ #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) -/* Host Bridge */ +/* Host Bridge: HOST_DEVID 0x157b */ #define HOST_DEV 0x2 #define HOST_FUNC 0 -#define HOST_DEVID 0x157b #define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC) #define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC) -/* PCIe GPP Bridge 0 */ +/* PCIe GPP Bridge 0: PCIE0_DEVID 0x157c */ #define PCIE0_DEV 0x2 #define PCIE0_FUNC 1 -#define PCIE0_DEVID 0x157c #define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC) #define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC) -/* PCIe GPP Bridge 1 */ +/* PCIe GPP Bridge 1: PCIE1_DEVID 0x157c */ #define PCIE1_DEV 0x2 #define PCIE1_FUNC 2 -#define PCIE1_DEVID 0x157c #define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC) #define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC) -/* PCIe GPP Bridge 2 */ +/* PCIe GPP Bridge 2: PCIE2_DEVID 0x157c */ #define PCIE2_DEV 0x2 #define PCIE2_FUNC 3 -#define PCIE2_DEVID 0x157c #define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC) #define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC) -/* PCIe GPP Bridge 3 */ +/* PCIe GPP Bridge 3: PCIE3_DEVID 0x157c */ #define PCIE3_DEV 0x2 #define PCIE3_FUNC 4 -#define PCIE3_DEVID 0x157c #define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC) #define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC) -/* PCIe GPP Bridge 4 */ +/* PCIe GPP Bridge 4: PCIE4_DEVID 0x157c */ #define PCIE4_DEV 0x2 #define PCIE4_FUNC 5 -#define PCIE4_DEVID 0x157c #define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) #define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) -/* Platform Security Processor */ +/* Platform Security Processor: PSP_DEVID 0x1578 */ #define PSP_DEV 0x8 #define PSP_FUNC 0 -#define PSP_DEVID 0x1578 #define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC) #define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC) -/* HD Audio 1 */ +/* HD Audio 1: HDA1_DEVID 0x157a */ #define HDA1_DEV 0x9 #define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) @@ -157,47 +147,44 @@ #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) -/* XHCI */ +/* XHCI: XHCI_DEVID 0x7914 */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x7914 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) -/* SATA */ +/* + * SATA: + * SATA_IDE_IDEVID 0x7900 + * AHCI_DEVID_MS 0x7901 + * AHCI_DEVID_AMD 0x7904 + */ #define SATA_DEV 0x11 #define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) -/* EHCI */ +/* EHCI: EHCI_DEVID 0x7908 */ #define EHCI_DEV 0x12 #define EHCI_FUNC 0 -#define EHCI_DEVID 0x7908 #define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) #define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) -/* SMBUS */ +/* SMBUS: SMBUS_DEVID 0x790b */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x790b #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) -/* LPC BUS */ +/* LPC BUS: LPC_DEVID 0x790e */ #define PCU_DEV 0x14 #define LPC_FUNC 3 -#define LPC_DEVID 0x790e #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -/* SD Controller */ +/* SD Controller: SD_DEVID 0x7906 */ #define SD_DEV 0x14 #define SD_FUNC 7 -#define SD_DEVID 0x7906 #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) -- To view, visit https://review.coreboot.org/c/coreboot/+/59268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b Gerrit-Change-Number: 59268 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot: Use default kernel secdata size
by Karthik Ramasubramanian (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Julius Werner, Yu-Ping Wu, Andrey Pronin. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58669 ) Change subject: security/vboot: Use default kernel secdata size ...................................................................... Patch Set 4: (1 comment) File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/c/coreboot/+/58669/comment/f9d88489_1394da48 PS3, Line 74: > I'd be nice to print an error message for errors other than TPM_E_READ_EMPTY. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Gerrit-Change-Number: 58669 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Correct WWAN power sequence
by Chen Wisley (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59267 to look at the new patch set (#2). Change subject: mb/google/brya/var/redrix: Correct WWAN power sequence ...................................................................... mb/google/brya/var/redrix: Correct WWAN power sequence Correct the WWAN power sequence to meet spec BUG=b:206079177 TEST=build Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix/include/variant/gpio.h 3 files changed, 29 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59267/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Gerrit-Change-Number: 59267 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/vboot: Use default kernel secdata size
by Karthik Ramasubramanian (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Julius Werner, Andrey Pronin, Karthik Ramasubramanian. Karthik Ramasubramanian has uploaded a new patch set (#4) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/58669 ) Change subject: security/vboot: Use default kernel secdata size ...................................................................... security/vboot: Use default kernel secdata size When fetching antirollback information for the kernel, it is not always known ahead of time what the current size of the kernel secdata area is. If the incorrect size is passed, the TPM will return back the correct size, but at the cost of an extra transaction; when using cr50 over I2C, this can be as much as 20ms. Currently, the first attempt uses the minimium size (aka version 0 or 0.2), and if another size is used (which is the case for all modern cr50-based boards, version 1 or 1.0), then a transaction is wasted on every boot. Therefore, change the default size sent to the TPM to be the default one used in the VB2 API instead of the minimum one. BUG=b:201304784 TEST=verify TPM initialization time drops by ~20ms. Also the Kernel NV Index is read correctly in the BIOS logs. src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 504:finished TPM initialization 99,953 (65,606) Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/secdata_tpm.c 1 file changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58669/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Gerrit-Change-Number: 58669 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/redrix: Correct WWAN power sequence
by build bot (Jenkins) (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak, Wisley Chen. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59267 ) Change subject: mb/google/brya/var/redrix: Correct WWAN power sequence ...................................................................... Patch Set 1: (7 comments) File src/mainboard/google/brya/variants/redrix/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133166): https://review.coreboot.org/c/coreboot/+/59267/comment/5a5a4d66_2a406106 PS1, Line 98: /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133166): https://review.coreboot.org/c/coreboot/+/59267/comment/c60e00fe_d875503d PS1, Line 125: /* B4 : PROC_GP3 ==> SSD_PERST_L */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133166): https://review.coreboot.org/c/coreboot/+/59267/comment/23eaf0fa_114c587a PS1, Line 126: PAD_CFG_GPO(GPP_B4, 1, DEEP), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133166): https://review.coreboot.org/c/coreboot/+/59267/comment/766d9d22_2dd545db PS1, Line 126: PAD_CFG_GPO(GPP_B4, 1, DEEP), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133166): https://review.coreboot.org/c/coreboot/+/59267/comment/b66a7cfe_e3227809 PS1, Line 127: /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133166): https://review.coreboot.org/c/coreboot/+/59267/comment/458cfca6_68d4ba70 PS1, Line 128: PAD_CFG_GPO(GPP_F21, 1, DEEP), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133166): https://review.coreboot.org/c/coreboot/+/59267/comment/665d2c3c_b856e1bd PS1, Line 128: PAD_CFG_GPO(GPP_F21, 1, DEEP), please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Gerrit-Change-Number: 59267 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 16:35:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021