coreboot-gerrit November 2021

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Change in coreboot[master]: google/butterfly: Refactor get_recovery_mode_switch()
by Kyösti Mälkki (Code Review) 12 Nov '21

12 Nov '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59003 ) Change subject: google/butterfly: Refactor get_recovery_mode_switch() ...................................................................... google/butterfly: Refactor get_recovery_mode_switch() Do not place console output in low-level GPIO functions. The caller of get_recovery_mode_switch() is in vboot_logic.c that is linked in romstage. So presumably recovery mode is broken and is not fixed with this commit either. Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59003 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/butterfly/chromeos.c 1 file changed, 4 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 2293f93..83b6ba0 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> @@ -13,8 +12,6 @@ #include "ec.h" #include "onboard.h" -#define FORCE_RECOVERY_MODE 0 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -42,23 +39,13 @@ return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; } +/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */ int get_recovery_mode_switch(void) { - int ec_rec_mode = 0; + if (ENV_RAMSTAGE) + return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO); - if (FORCE_RECOVERY_MODE) { - printk(BIOS_DEBUG, "FORCING RECOVERY MODE.\n"); - return 1; - } - - if (ENV_RAMSTAGE) { - if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) - ec_rec_mode = 1; - - printk(BIOS_DEBUG, "RECOVERY MODE FROM EC: %x\n", ec_rec_mode); - } - - return ec_rec_mode; + return 0; } static const struct cros_gpio cros_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Gerrit-Change-Number: 59003 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi/acpigen,soc/amd,cpu/inte: Refactor the code
by Michael Niewöhner (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Maulik V Vaghela, Sugnan Prabhu S, Tim Wawrzynczak, Sridhar Siricilla, Rob Barnes, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59125 ) Change subject: acpi/acpigen,soc/amd,cpu/inte: Refactor the code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59125/comment/18ee0de9_beb1002f PS1, Line 7: : I buy an `l` :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/59125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bdcf94973973dcf7b1ff915df6e23108c9b8ff9 Gerrit-Change-Number: 59125 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 19:21:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi/acpigen,soc/amd,cpu/inte: Refactor the code
by Michael Niewöhner (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Maulik V Vaghela, Sugnan Prabhu S, Tim Wawrzynczak, Sridhar Siricilla, Rob Barnes, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59125 ) Change subject: acpi/acpigen,soc/amd,cpu/inte: Refactor the code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59125/comment/e378047c_12ac9667 PS1, Line 9: The patch add below changes : : * Refactor the code to allow SoC vendor to implement their own _CPC : control method : * Move the definition of CPPC_PACKAGE_NAME macro into acpigen header file : to get called from soc/intel. : * Modify acpigen_write_CPPC_method() to accept core_id as an argument to : allow the _CPC control method to call GCPC method with core_id arg. : these are three separate changes -- To view, visit https://review.coreboot.org/c/coreboot/+/59125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bdcf94973973dcf7b1ff915df6e23108c9b8ff9 Gerrit-Change-Number: 59125 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Nov 2021 19:20:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: Update CPPCv3 Nominal Frequency entry
by Michael Niewöhner (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak, Sugnan Prabhu S, Ravindra, Sridhar Siricilla, Patrick Rudolph, Ravindra N. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57783 ) Change subject: cpu/intel/common: Update CPPCv3 Nominal Frequency entry ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57783/comment/f0f30491_73174166 PS7, Line 9: DWORD buffer there is no such thing, it can either be the one or the other File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/57783/comment/f4f129de_d694ead5 PS7, Line 136: CPPC_DWORD(0); > Isn't this functionally the same thing? the field reads back as zero, and the kernel interprets this […] The difference is: CPPC_UNSUPPORTED resulting in `{Register {(SystemMemory, 0, 0, 0, 0)}` which the OSPM interprets as `unsupported`, while `DWORD(0)` is interpreted as actual integer value `0`. However, depending on the implementation `0` could be interpreted as `unsupported`, too, for this specific field. Ravindra, elaborate, please From the ACPI spec: ``` Nominal Frequency Type: Integer (DWORD) or Buffer Optional. [...] If this element is an Integer, OSPM reads the integer value directly. If this element is a Buffer (and supported), it must contain a Resource Descriptor with a single Register() to read the value from. ``` ``` Optional _CPC package fields that are not supported by the platform should be encoded as follows: - Integer fields: Integer 0 - Register fields: the following NULL register descriptor should be used: ResourceTemplate() {Register {(SystemMemory, 0, 0, 0, 0)}} ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/57783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39e5e4ac77a71b143cdb5f043fb398abb398ee3 Gerrit-Change-Number: 57783 Gerrit-PatchSet: 7 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 19:19:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: google/stout: Remove duplicate recovery mode switch entry
by Julius Werner (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak, Kyösti Mälkki. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59192 ) Change subject: google/stout: Remove duplicate recovery mode switch entry ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465 Gerrit-Change-Number: 59192 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 19:18:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: google/butterfly: Refactor get_recovery_mode_switch()
by Julius Werner (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak, Stefan Reinauer, Kyösti Mälkki. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59003 ) Change subject: google/butterfly: Refactor get_recovery_mode_switch() ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: This board is from a time when vboot was still running in the payload (and this function only existed to pass the recovery mode state through lb_gpios, in ramstage). I assume recovery mode has been broken ever since we started pulling it into coreboot. We probably could as well remove Chrome OS support completely from this board now, I don't think anyone is ever going to bother fixing it up again. -- To view, visit https://review.coreboot.org/c/coreboot/+/59003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Gerrit-Change-Number: 59003 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 19:17:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Felix Held (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58871 ) Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Patchset: PS6: console log from bootblock on barla with the patch applied: coreboot-4.14-2624-g479492e3d6-dirty Wed Nov 10 10:40:56 UTC 2021 bootblock starting (log level: 7)... Family_Model: 00670f00 Set power off after power failure. PMxC0 STATUS: 0x80800 DoReset BIT11 SPI normal read speed: 16.66 MHz SPI fast read speed: 33.33 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Dual IO (1-1-2) I2C bus 1 version 0x3132312a DW I2C bus 1 at 0xfedc3000 (400 KHz) FMAP: Found "FLASH" version 1.1 at 0x10000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 4 FMAP: area COREBOOT found @ 10200 (16711168 bytes) CBFS: mcache @0x00035800 built for 18 files, used 0x3a8 of 0x4000 bytes CBFS: Found 'fallback/romstage' @0x80 size 0xa690 in mcache @0x0003582c BS: bootblock times (exec / console): total (unknown) / 65 ms -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 19:04:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Felix Held (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58871 ) Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: looks good to me and careena/barla still get to loading the payload like before when checking out this patch as a branch. probably the kconfig options for the efs spi read mode and speed should be set in the board's kconfig to the values used in src/mainboard/google/kahlee/bootblock/bootblock.c. see the zork or guybrush kconfig files for setting those options -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Nov 2021 18:59:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Felix Held (Code Review) 12 Nov '21

12 Nov '21

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Change in coreboot[master]: soc/intel/alderlake: Allow thermal configuration for ADL
by Subrata Banik (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59271 ) Change subject: soc/intel/alderlake: Allow thermal configuration for ADL ...................................................................... soc/intel/alderlake: Allow thermal configuration for ADL Thermal configuration registers are now located behind PMC PWRMBASE for Alder Lake Point PCH. Hence, ADL SoC to select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold is being set as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. BUG=b:193774296 TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/59271/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 58b9051..796f7bc 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -68,6 +68,8 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index ae28d18..4e1b47f 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -10,6 +10,7 @@ #include <intelblocks/irq.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> +#include <intelblocks/thermal.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> @@ -129,6 +130,15 @@ void soc_init_pre_device(void *chip_info) { + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and LTT >= DTS Temp. + */ + pch_thermal_configuration(); + /* Perform silicon specific init. */ fsp_silicon_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/59271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Gerrit-Change-Number: 59271 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021