coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Kyösti Mälkki (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Дмитрий Понаморев, Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, King Sumo. Kyösti Mälkki has uploaded a new patch set (#19) to the change originally created by Дмитрий Понаморев. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 These sources are to compile the coreboot firmware image for the teleplatforms D4E4S16P8 motherboard. The board is based on an Intel Atom C3758 processor. Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Signed-off-by: Dmitry Ponamorev <dponamorev(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A configs/config.teleplatforms.D4E4S16P8 A src/mainboard/teleplatforms/D4E4S16P8/Kconfig A src/mainboard/teleplatforms/D4E4S16P8/Kconfig.name A src/mainboard/teleplatforms/D4E4S16P8/Makefile.inc A src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard_pci_irqs.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/platform.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/thermal.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi_tables.c A src/mainboard/teleplatforms/D4E4S16P8/board_info.txt A src/mainboard/teleplatforms/D4E4S16P8/devicetree.cb A src/mainboard/teleplatforms/D4E4S16P8/dsdt.asl A src/mainboard/teleplatforms/D4E4S16P8/hsio.c A src/mainboard/teleplatforms/D4E4S16P8/ramstage.c A src/mainboard/teleplatforms/D4E4S16P8/romstage.c A src/mainboard/teleplatforms/Kconfig A src/mainboard/teleplatforms/Kconfig.name 17 files changed, 1,772 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/57194/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 19 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by EricR Lai (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 11:40:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal Shutdown
by EricR Lai (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59270 ) Change subject: soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal Shutdown ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79 Gerrit-Change-Number: 59270 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 11:38:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up common code for thermal configuration
by EricR Lai (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Felix Singer, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59271 ) Change subject: soc/intel/alderlake: Hook up common code for thermal configuration ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: Bray can boot and reboot without issues. -- To view, visit https://review.coreboot.org/c/coreboot/+/59271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Gerrit-Change-Number: 59271 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 11:36:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Compile IA common thermal block in romstage
by EricR Lai (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59391 ) Change subject: soc/intel/../thermal: Compile IA common thermal block in romstage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8 Gerrit-Change-Number: 59391 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 11:36:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/brya: Enable dev screen in bios-stage for Brask
by Alan Huang (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Tim Wawrzynczak, Adam Liu. Alan Huang has uploaded a new patch set (#3) to the change originally created by Adam Liu. ( https://review.coreboot.org/c/coreboot/+/59414 ) Change subject: mainboard/google/brya: Enable dev screen in bios-stage for Brask ...................................................................... mainboard/google/brya: Enable dev screen in bios-stage for Brask Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION and its dependencies. TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage. BUG=b:199490251, b:206014054 Signed-off-by: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 --- M src/mainboard/google/brya/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59414/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 Gerrit-Change-Number: 59414 Gerrit-PatchSet: 3 Gerrit-Owner: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: clean up psp fw parsing
by Kangheui Won (Code Review) 18 Nov '21

18 Nov '21

Kangheui Won has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59449 ) Change subject: amdfwtool: clean up psp fw parsing ...................................................................... amdfwtool: clean up psp fw parsing find_register_fw_filename_psp_dir parses first token from the fw.cfg and find fw_type and subprog for it. However every entries are hard-coded, which makes code to be hard to read and maintain. Make a new lookup table so things are more organized than before. TEST=build guybrush and confirm amdfw and coreboot.rom are identical Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c --- M util/amdfwtool/data_parse.c 1 file changed, 80 insertions(+), 176 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59449/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c Gerrit-Change-Number: 59449 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: clean up psp fw parsing
by build bot (Jenkins) (Code Review) 18 Nov '21

18 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59449 ) Change subject: amdfwtool: clean up psp fw parsing ...................................................................... Patch Set 1: (11 comments) File util/amdfwtool/data_parse.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/67b262b4_b73bd826 PS1, Line 179: if (!cb_config->have_whitelist) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/19935cc8_8862a28a PS1, Line 183: if (!cb_config->unlock_secure) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/c3608671_7a23d790 PS1, Line 187: if (!cb_config->unlock_secure) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/6ceb0b65_41763817 PS1, Line 191: if (!cb_config->use_secureos) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/2d36631d_4dfcafc5 PS1, Line 195: if (!cb_config->use_secureos) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/55db8917_0bed0c10 PS1, Line 199: if (!cb_config->use_secureos) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/cf773691_a6f2082c PS1, Line 203: if (!cb_config->load_mp2_fw) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/8817608a_2d75cf66 PS1, Line 207: if (!cb_config->load_mp2_fw) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/81800ebd_8a5a65ac PS1, Line 211: if (!cb_config->load_mp2_fw) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/b01d5387_669eff51 PS1, Line 215: if (!cb_config->s0i3) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133706): https://review.coreboot.org/c/coreboot/+/59449/comment/6937cdf7_9d586163 PS1, Line 219: if (cb_config->have_whitelist) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/59449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c Gerrit-Change-Number: 59449 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 18 Nov 2021 10:05:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: clean up psp fw parsing
by Kangheui Won (Code Review) 18 Nov '21

18 Nov '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59449 ) Change subject: amdfwtool: clean up psp fw parsing ...................................................................... amdfwtool: clean up psp fw parsing find_register_fw_filename_psp_dir parses first token from the fw.cfg and find fw_type and subprog for it. However every entries are hard-coded, which makes code to be hard to read and maintain. Make a new lookup table so things are more organized than before. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c --- M util/amdfwtool/data_parse.c 1 file changed, 80 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59449/1 diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 8f93183..442155e 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -9,6 +9,8 @@ #include "amdfwtool.h" +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + /* TODO: a empty line does not matched. */ static const char blank_or_comment_regex[] = /* a blank line */ @@ -100,210 +102,123 @@ extern amd_fw_entry amd_psp_fw_table[]; extern amd_bios_entry amd_bios_table[]; +struct psp_valid_entry_table { + const char *fw_name; + amd_fw_type fw_type; + uint8_t subprog; +}; +static const struct psp_valid_entry_table psp_dir_valid_entries[] = { + {"PSPBTLDR_WL_FILE", AMD_FW_PSP_BOOTLOADER_AB, 0}, + {"PSPBTLDR_FILE", AMD_FW_PSP_BOOTLOADER, 0}, + {"AMD_PUBKEY_FILE", AMD_FW_PSP_PUBKEY, 0}, + {"PSPRCVR_FILE", AMD_FW_PSP_RECOVERY, 0}, + {"PUBSIGNEDKEY_FILE", AMD_FW_PSP_RTM_PUBKEY, 0}, + {"PSPNVRAM_FILE", AMD_FW_PSP_NVRAM, 0}, + {"SMUSCS_FILE", AMD_FW_PSP_SMUSCS, 0}, + {"PSPTRUSTLETS_FILE", AMD_FW_PSP_TRUSTLETS, 0}, + {"PSPSECUREDEBUG_FILE", AMD_FW_PSP_SECURED_DEBUG, 0}, + {"PSP_SMUFW1_SUB0_FILE", AMD_FW_PSP_SMU_FIRMWARE, 0}, + {"PSP_HW_IPCFG_FILE", AMD_HW_IPCFG, 0}, + {"PSP_SMUFW1_SUB1_FILE", AMD_FW_PSP_SMU_FIRMWARE, 1}, + {"PSP_SMUFW1_SUB2_FILE", AMD_FW_PSP_SMU_FIRMWARE, 2}, + {"PSP_SMUFW2_SUB0_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 0}, + {"PSP_SMUFW2_SUB1_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 1}, + {"PSP_SMUFW2_SUB2_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 2}, + {"PSP_SEC_DBG_KEY_FILE", AMD_FW_PSP_SECURED_DEBUG, 0}, + {"PSP_SEC_DEBUG_FILE", AMD_DEBUG_UNLOCK, 0}, + {"PSP_ABL0_FILE", AMD_ABL0, 0}, + {"PSP_ABL1_FILE", AMD_ABL1, 0}, + {"PSP_ABL2_FILE", AMD_ABL2, 0}, + {"PSP_ABL3_FILE", AMD_ABL3, 0}, + {"PSP_ABL4_FILE", AMD_ABL4, 0}, + {"PSP_ABL5_FILE", AMD_ABL5, 0}, + {"PSP_ABL6_FILE", AMD_ABL6, 0}, + {"PSP_ABL7_FILE", AMD_ABL7, 0}, + {"PSPSECUREOS_FILE", AMD_FW_PSP_SECURED_OS, 0}, + {"PSPTRUSTLETS_FILE", AMD_FW_PSP_TRUSTLETS, 0}, + {"TRUSTLETKEY_FILE", AMD_FW_PSP_TRUSTLETKEY, 0}, + {"PSP_IKEK_FILE", AMD_WRAPPED_IKEK, 0}, + {"PSP_SECG0_FILE", AMD_SEC_GASKET, 0}, + {"PSP_SECG1_FILE", AMD_SEC_GASKET, 1}, + {"PSP_SECG2_FILE", AMD_SEC_GASKET, 2}, + {"PSP_MP2FW0_FILE", AMD_MP2_FW, 0}, + {"PSP_MP2FW1_FILE", AMD_MP2_FW, 1}, + {"PSP_MP2FW2_FILE", AMD_MP2_FW, 2}, + {"PSP_DRIVERS_FILE", AMD_DRIVER_ENTRIES, 0}, + {"PSP_S0I3_FILE", AMD_S0I3_DRIVER, 0}, + {"AMD_DRIVER_ENTRIES", AMD_DRIVER_ENTRIES, 0}, + {"VBIOS_BTLOADER_FILE", AMD_VBIOS_BTLOADER, 0}, + {"SECURE_POLICY_L1_FILE", AMD_FW_TOS_SEC_POLICY, 0}, + {"UNIFIEDUSB_FILE", AMD_FW_USB_PHY, 0}, + {"DRTMTA_FILE", AMD_FW_DRTM_TA, 0}, + {"KEYDBBL_FILE", AMD_FW_KEYDB_BL, 0}, + {"KEYDB_TOS_FILE", AMD_FW_KEYDB_TOS, 0}, + {"DMCUERAMDCN21_FILE", AMD_FW_DMCU_ERAM, 0}, + {"DMCUINTVECTORSDCN21_FILE", AMD_FW_DMCU_ISR, 0}, + {"PSP_KVM_ENGINE_DUMMY_FILE", AMD_FW_KVM_IMAGE, 0}, + {"RPMC_FILE", AMD_RPMC_NVRAM, 0}, + {"PSPBTLDR_AB_FILE", AMD_FW_PSP_BOOTLOADER_AB, 0} +}; + static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, char level_to_set, amd_cb_config *cb_config) { amd_fw_type fw_type = AMD_FW_INVALID; amd_fw_entry *psp_tableptr; - uint8_t subprog; + uint8_t subprog = 0; + unsigned long i = 0; + for (i = 0; i < ARRAY_SIZE(psp_dir_valid_entries); i++) { + if (strcmp(fw_name, psp_dir_valid_entries[i].fw_name) == 0) { + fw_type = psp_dir_valid_entries[i].fw_type; + subprog = psp_dir_valid_entries[i].subprog; + break; + } + } if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { - if (cb_config->have_whitelist) { - fw_type = AMD_FW_PSP_BOOTLOADER_AB; - subprog = 0; - } else { + if (!cb_config->have_whitelist) { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { - fw_type = AMD_FW_PSP_BOOTLOADER; - subprog = 0; - } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { - fw_type = AMD_FW_PSP_PUBKEY; - subprog = 0; - } else if (strcmp(fw_name, "PSPRCVR_FILE") == 0) { - fw_type = AMD_FW_PSP_RECOVERY; - subprog = 0; - } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) { - fw_type = AMD_FW_PSP_RTM_PUBKEY; - subprog = 0; - } else if (strcmp(fw_name, "PSPNVRAM_FILE") == 0) { - fw_type = AMD_FW_PSP_NVRAM; - subprog = 0; - } else if (strcmp(fw_name, "SMUSCS_FILE") == 0) { - fw_type = AMD_FW_PSP_SMUSCS; - subprog = 0; - } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { - fw_type = AMD_FW_PSP_TRUSTLETS; - subprog = 0; - } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { - fw_type = AMD_FW_PSP_SECURED_DEBUG; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE; - subprog = 0; - } else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE") == 0) { - fw_type = AMD_HW_IPCFG; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE; - subprog = 1; - } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE; - subprog = 2; - } else if (strcmp(fw_name, "PSP_SMUFW2_SUB0_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE2; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE2; - subprog = 1; - } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { - fw_type = AMD_FW_PSP_SMU_FIRMWARE2; - subprog = 2; } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { - if (cb_config->unlock_secure) { - fw_type = AMD_FW_PSP_SECURED_DEBUG; - subprog = 0; - } else { + if (!cb_config->unlock_secure) { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { - if (cb_config->unlock_secure) { - fw_type = AMD_DEBUG_UNLOCK; - subprog = 0; - } else { + if (!cb_config->unlock_secure) { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) { - fw_type = AMD_ABL0; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) { - fw_type = AMD_ABL1; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) { - fw_type = AMD_ABL2; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) { - fw_type = AMD_ABL3; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) { - fw_type = AMD_ABL4; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) { - fw_type = AMD_ABL5; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) { - fw_type = AMD_ABL6; - subprog = 0; - } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) { - fw_type = AMD_ABL7; - subprog = 0; } else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) { - if (cb_config->use_secureos) { - fw_type = AMD_FW_PSP_SECURED_OS; - subprog = 0; - } else { + if (!cb_config->use_secureos) { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { - if (cb_config->use_secureos) { - fw_type = AMD_FW_PSP_TRUSTLETS; - subprog = 0; - } else { + if (!cb_config->use_secureos) { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "TRUSTLETKEY_FILE") == 0) { - if (cb_config->use_secureos) { - fw_type = AMD_FW_PSP_TRUSTLETKEY; - subprog = 0; - } else { + if (!cb_config->use_secureos) { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { - fw_type = AMD_WRAPPED_IKEK; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SECG0_FILE") == 0) { - fw_type = AMD_SEC_GASKET; - subprog = 0; - } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { - fw_type = AMD_SEC_GASKET; - subprog = 1; - } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { - fw_type = AMD_SEC_GASKET; - subprog = 2; } else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) { - if (cb_config->load_mp2_fw) { - fw_type = AMD_MP2_FW; - subprog = 0; - } else { + if (!cb_config->load_mp2_fw) { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { - if (cb_config->load_mp2_fw) { - fw_type = AMD_MP2_FW; - subprog = 1; - } else { + if (!cb_config->load_mp2_fw) { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { - if (cb_config->load_mp2_fw) { - fw_type = AMD_MP2_FW; - subprog = 2; - } else { + if (!cb_config->load_mp2_fw) { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { - fw_type = AMD_DRIVER_ENTRIES; - subprog = 0; } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { - if (cb_config->s0i3) { - fw_type = AMD_S0I3_DRIVER; - subprog = 0; - } else { + if (!cb_config->s0i3) { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "AMD_DRIVER_ENTRIES") == 0) { - fw_type = AMD_DRIVER_ENTRIES; - subprog = 0; - } else if (strcmp(fw_name, "VBIOS_BTLOADER_FILE") == 0) { - fw_type = AMD_VBIOS_BTLOADER; - subprog = 0; - } else if (strcmp(fw_name, "SECURE_POLICY_L1_FILE") == 0) { - fw_type = AMD_FW_TOS_SEC_POLICY; - subprog = 0; - } else if (strcmp(fw_name, "UNIFIEDUSB_FILE") == 0) { - fw_type = AMD_FW_USB_PHY; - subprog = 0; - } else if (strcmp(fw_name, "DRTMTA_FILE") == 0) { - fw_type = AMD_FW_DRTM_TA; - subprog = 0; - } else if (strcmp(fw_name, "KEYDBBL_FILE") == 0) { - fw_type = AMD_FW_KEYDB_BL; - subprog = 0; - } else if (strcmp(fw_name, "KEYDB_TOS_FILE") == 0) { - fw_type = AMD_FW_KEYDB_TOS; - subprog = 0; - } else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) { - fw_type = AMD_FW_DMCU_ERAM; - subprog = 0; - } else if (strcmp(fw_name, "DMCUINTVECTORSDCN21_FILE") == 0) { - fw_type = AMD_FW_DMCU_ISR; - subprog = 0; - } else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) { - fw_type = AMD_FW_KVM_IMAGE; - subprog = 0; - } else if (strcmp(fw_name, "RPMC_FILE") == 0) { - fw_type = AMD_RPMC_NVRAM; - subprog = 0; } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { - if (!cb_config->have_whitelist) { - fw_type = AMD_FW_PSP_BOOTLOADER_AB; - subprog = 0; - } else { + if (cb_config->have_whitelist) { fw_type = AMD_FW_SKIP; } - } else { - fw_type = AMD_FW_INVALID; - /* TODO: Add more */ } /* Search and fill the filename */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c Gerrit-Change-Number: 59449 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Do not check for RW partitions if not part of the image
by Werner Zeh (Code Review) 18 Nov '21

18 Nov '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31662 Change subject: security/vboot: Do not check for RW partitions if not part of the image ...................................................................... security/vboot: Do not check for RW partitions if not part of the image In the setup where measured boot is used with read-only partition only there is no RW_A or RW_B partition in the flash. In this case it makes no sense to let VBOOT check for these partitions just to fail and then fall back to recovery mode. Instead set the flag VB2_CONTEXT_RECOVERY_MODE right away so that VBOOT starts in recovery mode any time. This kind of bypasses VBOOT logic but is still suitable to have a pure measured boot scheme enabled. In addition it avoids the first two reboots due to missing RW_A and RW_B. Change-Id: I07b8ec97be7db63b7ccddb3f33e0f741bed8acd8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/31662/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 8c3ba80..89934b9 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -324,6 +324,12 @@ die("Initializing measured boot mode failed!"); } + /* Skip checking for RW_A and RW_B if these partitions are not included + in the image. Instead proceed with recovery mode which uses RO + partition only. */ + if (!IS_ENABLED(CONFIG_VBOOT_SLOTS_RW_A)) + ctx.flags |= VB2_CONTEXT_RECOVERY_MODE; + if (IS_ENABLED(CONFIG_VBOOT_PHYSICAL_DEV_SWITCH) && get_developer_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; -- To view, visit https://review.coreboot.org/c/coreboot/+/31662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07b8ec97be7db63b7ccddb3f33e0f741bed8acd8 Gerrit-Change-Number: 31662 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021