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Change subject: [TEST] Updating FSP Binary repo path
......................................................................
Removed reviewer Patrick Rudolph.
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Change subject: doc/mb/ocp: update Delta Lake documentation
......................................................................
doc/mb/ocp: update Delta Lake documentation
Update Delta Lake document following the publish of OCP blog
and the Wiwynn press release.
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Change-Id: I3eaa765bf9918988b4b5cb01e8607a5c27b9bd17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58979
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Reviewed-by: Christian Walter <christian.walter(a)9elements.com>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Documentation/mainboard/ocp/deltalake.md
1 file changed, 14 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Christian Walter: Looks good to me, approved
Johnny Lin: Looks good to me, but someone else must approve
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md
index 8906ad8..3f80538 100644
--- a/Documentation/mainboard/ocp/deltalake.md
+++ b/Documentation/mainboard/ocp/deltalake.md
@@ -7,7 +7,16 @@
OCP Delta Lake server platform is a component of multi-host server system
Yosemite-V3. Both [Delta Lake server design spec] and [Yosemite-V3 design
-spec] were contributed to [OCP].
+spec] were [OCP] accepted.
+
+On the other hand, Wiwynn's Yosemite-V3 system and Delta Lake server product
+along with its OSF implementation, which is based on FSP/coreboot/LinuxBoot
+stack, was [OCP] accepted; For details, check:
+- [The OCP blog]
+- [The Wiwynn Press Release]
+- [The Wiwynn's Yosemite-V3 product in OCP market place]
+Wiwynn and 9Elements formed a partnership to offer the Wiwynn's Yosemite-V3
+product and OSF for it.
Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
Intel Cooper Lake Scalable Processor was launched in Q2 2020.
@@ -15,7 +24,7 @@
Yosemite-V3 has multiple configurations. Depending on configurations, it may
host up to 4 Delta Lake servers (blades) in one sled.
-The Yosemite-V3 system is in mass production. Facebook, Intel and partners
+The Yosemite-V3 system is in mass production. Meta, Intel and partners
jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
OSF solution reached production quality for some use cases in July, 2021.
@@ -187,6 +196,9 @@
[OCP]: https://www.opencompute.org
[Delta Lake server design spec]: https://www.opencompute.org/documents/delta-lake-1s-server-design-specifica…
[Yosemite-V3 design spec]: https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-speci…
+[The OCP blog]: https://www.opencompute.org/blog/open-system-firmware-for-ocp-server-deltal…
+[The Wiwynn Press Release]: https://www.prnewswire.com/news-releases/wiwynn-successfully-implemented-op…
+[The Wiwynn's Yosemite-V3 product in OCP market place]: https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server
[osf-builder]: https://github.com/facebookincubator/osf-builder
[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
[flashrom]: https://flashrom.org/Flashrom
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Change subject: doc/mb/ocp: update Delta Lake documentation
......................................................................
Patch Set 2: Code-Review+2
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 )
Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
......................................................................
Patch Set 19:
(6 comments)
File src/mainboard/teleplatforms/D4E4S16P8/Kconfig:
https://review.coreboot.org/c/coreboot/+/57194/comment/d151c591_4c33f0c0
PS17, Line 14: ##
> I'll adjust the licenses to one-liners.
Done
File src/mainboard/teleplatforms/D4E4S16P8/Kconfig:
https://review.coreboot.org/c/coreboot/+/57194/comment/a1a67915_13f2e5fd
PS19, Line 31: default "1.0.12"
This should be explicitly set only for a release to avoid mistaking development builds as releases. Seems like src/Kconfig:config LOCALVERSION will achieve the same thing.
File src/mainboard/teleplatforms/D4E4S16P8/gpio.h:
https://review.coreboot.org/c/coreboot/+/57194/comment/fb54c321_d29a2e7f
PS18, Line 9: const struct dnv_pad_config D4E4S16P8_gpio_table[] = {
> No data, only prototypes and defines in .h files.
Done
File src/mainboard/teleplatforms/D4E4S16P8/hsio.h:
https://review.coreboot.org/c/coreboot/+/57194/comment/e902a849_7d0e4b09
PS18, Line 9: const BL_HSIO_INFORMATION D4E4S16P8_hsio_config[] = {
> No data, only prototypes and defines in .h files.
Done
File src/mainboard/teleplatforms/D4E4S16P8/ramstage.c:
https://review.coreboot.org/c/coreboot/+/57194/comment/ddcbf45f_0d129759
PS18, Line 28: if (tmp == 0x3f/*?*/ || (tmp < 0x20 || tmp > 0x7f)) {
> I'll recude this to BIOS_SPEW. […]
Done
File src/mainboard/teleplatforms/D4E4S16P8/smbus.c:
https://review.coreboot.org/c/coreboot/+/57194/comment/2e709a89_ce4d6f5c
PS17, Line 81: .device = 0x19df, /* Denverton SMBus0 "Legacy" device id */
> This file is not specific to your board, I'll remove it here. […]
Done
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Hello build bot (Jenkins), Дмитрий Понаморев, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36607
to look at the new patch set (#12).
Change subject: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
......................................................................
[WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
Configure graphics PCI device as VGA using software bootstrap
bits.
TBD: Can we delay this to be done as a common PCI driver.
TBD: Add Kconfig guard.
Change-Id: I92195969419f9c38845cb67f294fdab33fb481af
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/teleplatforms/D4E4S16P8/Makefile.inc
A src/mainboard/teleplatforms/D4E4S16P8/ast25xx.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/denverton_ns/include/soc/ramstage.h
4 files changed, 208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36607/12
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